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Epson Research and Development
Vancouver Design Center
REG[048h] LCD Pixel Panning Register
LCD Pixel
Panning Bit 1 Panning Bit 0
LCD Pixel
n/a
n/a
n/a
n/a
n/a
Reserved
Reserved
Reserved
Reserved
REG[068h] CRT/TV Pixel Panning Register
CRT/TV Pixel CRT/TV Pixel
Panning Bit 1 Panning Bit 0
n/a
n/a
n/a
The pixel panning register offers finer control over panning than is available using the start
address registers. Using the pixel panning register, it is possible to pan the displayed image
one pixel at a time. The number of bits required to pan a single pixel at a time, change with
the color depth. The following table shows the bits of the pixel pan register which are used
for each color depth.
Table 5-2: Active Pixel Pan Bits
Color Depth (bpp) Pixel Pan bits used
4
8
bits [1:0]
bit 0
15/16
none
Note
The pixel panning registers are not required for color depths of 15 or 16 bpp.
The pixel panning registers must be updated in conjunction with the start address registers.
The pixel panning registers can be thought of as the least significant bit(s) of the start
address registers.
When panning to the right on an LCD set for a color depth of 4 bpp, the registers would be
updated as follows.
1. Pan right by 1 pixel - increment the pixel panning register by 1: REG[048h] = 01b.
2. Pan right by 1 pixel - increment the pixel panning register by 1: REG[048h] = 10b.
3. Pan right by 1 pixel - increment the pixel panning register by 1: REG[048h] = 11b.
4. Pan right by 1 pixel - reset the pixel panning register to 0: REG[048h] = 00b.
- increment the start address register by 1: (REG[042h],
REG[043h], REG[044h]) + 1.
Note
The above example assumes the pixel panning register is initially set at 0.
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
EPSON [ EPSON COMPANY ]
