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Epson Research and Development
Vancouver Design Center
5.2 Panning and Scrolling
The terms panning and scrolling refer to the actions used to move a viewport about a virtual
display. Although the entire image is stored in the display buffer, only a portion is visible
at any given time.
Panning describes the horizontal (side to side) motion of the viewport. When panning to the
right the image in the viewport appears to slide to the left. When panning to the left the
image to appears to slide to the right. Scrolling describes the vertical (up and down) motion
of the viewport. Scrolling down causes the image to appear to slide up and scrolling up
causes the image to appear to slide down.
Both panning and scrolling are performed by modifying the start address registers. The start
address refers to the word offset in the display buffer where the beginning of the image is
displayed from. At color depths less than 15 bpp, another register is required for smooth
movement. The pixel pan registers (REG[048h] for LCD, REG[068h] for CRT/TV) allow
panning in smaller increments than changing the start address alone.
Internally, the S1D13506 latches different signals at different times. Due to this internal
sequence, the start address and pixel pan registers should be accessed in a specific order
during panning and scrolling operations, in order to provide the smoothest scrolling. Setting
the registers in the wrong sequence, or at the wrong time, results in a “tearing” or jitter
effect on the display.
The start address is latched at the beginning of each frame, so the start address can be set
within the vertical non-display period (VNDP). The pixel pan register values are latched at
the beginning of each display line and must be set during the vertical non-display period.
The correct sequence for programing these registers is:
1. Wait for the beginning of the vertical non-display period - For the LCD, REG[03Ah]
bit 7 will return a 1 during VNDP; for the CRT/TV, REG[058h] bit 7 will return a 1
during VNDP. Wait for the transition of the appropriate bit to go from 0 to 1. This en-
sures the register updates are carried out at the beginning of VNDP.
2. Update the start address registers - For the LCD, REG[042h], REG[043h],
REG[044h]; for the CRT/TV, REG[062h], REG[063h], REG[064h].
3. Update the pixel panning register - For the LCD, REG[048h] bits 1-0; for the CRT/TV
REG[068h] bits 1-0.
Sample code for panning and scrolling is available in the file hal_virt.c which is included
in the HAL source code available on the internet at www.eea.epson.com.
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
EPSON [ EPSON COMPANY ]
