Epson Research and Development
Page 157
Vancouver Design Center
LCD Ink/Cursor FIFO High Threshold Register
REG[07Eh]
RW
LCD
LCD
LCD
LCD
Ink/Cursor
FIFO High
Threshold
Bit 3
Ink/Cursor
FIFO High
Threshold
Bit 2
Ink/Cursor
FIFO High
Threshold
Bit 1
Ink/Cursor
FIFO High
Threshold
Bit 0
n/a
n/a
n/a
n/a
bits 5-0
LCD Ink/Cursor FIFO High Threshold Bits [3:0]
These bits are used to optimize the display memory request arbitration for the Hardware
Cursor/Ink Layer. When this register is set to 00h, the threshold is automatically set in
hardware.
8.3.11 CRT/TV Ink/Cursor Registers
CRT/TV Ink/Cursor Control Register
REG[080h]
RW
CRT/TV
Ink/Cursor
Mode
CRT/TV
Ink/Cursor
Mode
n/a
n/a
n/a
n/a
n/a
n/a
Bit 1
Bit 0
bits 1-0
CRT/TV Ink/Cursor Control Bits [1:0]
These bits enable the CRT/TV Ink/Cursor circuitry.
Table 8-27: CRT/TV Ink/Cursor Selection
CRT/TV Ink/Cursor Bits [1:0]
Mode
Inactive
Cursor
Ink
00
01
10
11
Reserved
Note
During Ink mode, the Cursor X & Y Position registers must be programmed to zero.
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
EPSON [ EPSON COMPANY ]
