Page 102
Epson Research and Development
Vancouver Design Center
7.5.8 Dual Monochrome 8-Bit Panel Timing
VDP
VNDP
FPFRAME
FPLINE
DRDY (MOD)
LINE 1/241
LINE 2/242
LINE 3/243
LINE 4/244
LINE 239/479 LINE 240/480
LINE 1/241
LINE 2/242
FPDAT[7:0]
FPLINE
DRDY (MOD)
HNDP
HDP
FPSHIFT
1-637
1-638
1-1
1-5
FPDAT7
FPDAT6
1-2
1-3
1-6
1-639
1-7
1-8
FPDAT5
FPDAT4
FPDAT3
FPDAT2
1-4
1-640
241-1
241-2
241-3
241-4
241-5
241-6
241-637
241-638
241-639
241-640
241-7
241-8
FPDAT1
FPDAT0
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640x480 panel
Figure 7-37: Dual Monochrome 8-Bit Panel Timing
VDP
VNDP
HDP
= Vertical Display Period
= (REG[039h] bits [1:0], REG[038h] bits [7:1])
= (REG[03Ah] bits [5:0]) + 1
= ((REG[032h] bits [6:0]) + 1) × 8 Ts
= ((REG[034h] bits [4:0]) + 1) × 8 Ts
= Vertical Non-Display Period
= Horizontal Display Period
= Horizontal Non-Display Period
HNDP
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
EPSON [ EPSON COMPANY ]
