EM47FM3288SBB
AC Operating Test Characteristics
(VDD, VDDQ=1.5V±0.075V)
-125
(DDR3-1600)
-150
(DDR3-1333)
Speed Bin
Symbol
Units Notes
CL-nRCD-nRP
11-11-11
9-9-9
Parameter
Min.
Max.
Min.
Max.
-
DQS falling edge hold time from
tCK
(avg)
tDSH
0.18
-
0.2
29
rising CK
DQS falling edge setup time to rising
CK
tCK
(avg)
tDSS
tDQSL
tQSH
0.18
0.45
0.40
0.40
-
0.2
-
29
tCK
(avg)
DQS input low pulse width
DQS output high time
0.55
0.45
0.40
0.40
0.55
26,28
12,13
12,13
tCK
(avg)
-
-
-
-
tCK
(avg)
tQSL
DQS output low time
tMRD
Mode register set command cycle
4
-
-
-
4
-
-
-
nCK
ns
15
12
15
12
Mode register set command update
delay
tMOD
nCK
tCK
(avg)
tRPRE
tRPST
tWPRE
Read preamble time
Read postamble time
Write preamble time
0.9
0.3
0.9
-
-
-
0.9
0.3
0.9
-
-
-
13,19
11,13
1
tCK
(avg)
tCK
(avg)
tCK
(avg)
tWPST
tWR
Write postamble time
Write recovery time
0.3
15
-
-
0.3
15
-
-
1
ns
Auto precharge write recovery +
precharge time
tDAL(min)
tMPRR
WR + roundup[tRP / tCK(avg)]
nCK
Multi purpose register recovery time
1
7.5
4
-
-
-
-
-
1
7.5
4
-
-
-
-
-
nCK
ns
22
18
tWTR
Internal write to read command delay
nCK
ns
7.5
4
7.5
4
Internal read to precharge command
delay
tRTP
nCK
Minimum CKE low width for self-
refresh entry to exit
tCKE (min)
+1
tCKE (min)
+1
tCKESR
tCKSRE
-
-
nCK
10
5
-
-
-
-
10
5
-
-
-
-
ns
nCK
ns
Valid clock requirement after self-
refresh entry or power-down entry
10
5
10
5
Valid clock requirement before self-
refresh exit or power-down exit
tCKSRX
nCK
Jul. 2012
20/41
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EOREX [ EOREX CORPORATION ]
