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EM42BM3284LBA_09 参数 Datasheet PDF下载

EM42BM3284LBA_09图片预览
型号: EM42BM3284LBA_09
PDF下载: 下载PDF文件 查看货源
内容描述: 1GB ( 8M × 4Bank × 32 ),双倍数据速率SDRAM [1Gb (8M×4Bank×32) Double DATA RATE SDRAM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 24 页 / 1075 K
品牌: EOREX [ EOREX CORPORATION ]
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eorex  
EM42BM3284LBA  
Pin Description (Simplified)  
Pin  
Name  
Function  
(System Clock)  
Clock input active on the Positive rising edge except for DQ and  
DM are active on both edge of the DQS.  
CLK and /CLK are differential clock inputs.  
(Chip Select)  
G2,G3  
CLK,/CLK  
/CS enables the command decoder when ”L” and disable the  
command decoder when “H”.The new command are over-  
Looked when the command decoder is disabled but previous  
operation will still continue.  
H7  
G1  
/CS  
(Clock Enable)  
Activates the CLK when “H” and deactivates when “L”.  
When deactivate the clock,CKE low signifies the power down or  
self refresh mode.  
CKE  
(Address)  
J8,J9,K7,K9,K1,  
K3,J1~J3,H1~H3,  
Row address (A0 to A12) and Calumn address (CA0 to CA9) are  
multiplexed on the same pin.  
A0~12  
CA10 defines auto precharge at Calumn address.  
(Bank Address)  
Selects which bank is to be active.  
H8,H9  
G9  
BA0, BA1  
/RAS  
(Row Address Strobe)  
Latches Row Addresses on the positive rising edge of the CLK with  
/RAS “L”. Enables row access & pre-charge.  
(Column Address Strobe)  
G8  
/CAS  
Latches Column Addresses on the positive rising edge of the CLK  
with /CAS low. Enables column access.  
(Write Enable)  
G7  
/WE  
Latches Column Addresses on the positive rising edge of the CLK  
with /CAS low. Enables column access.  
(Data Input/Output)  
Data Inputs and Outputs are synchronized with both edge of DQS.  
(Data Input/Output Mask)  
L8,L2,E8,E2  
K8,K2,F8,F2  
DQS0~3  
DM0~3  
DM controls data inputs.DM0 corresponds to the data on  
DQ0~DQ7.DM1 corresponds to the data on DQ8~DQ15……..  
R8,P7,P8,N7,N8,M7,  
M8,L7,L3,M2,M3,N2,  
N3,P2,P3,R2,A8,B7,  
B8,C7,C8,D7,D8,E7,  
E3,D2,D3,C2,C3,B2,  
B3,A2  
(Data Input/Output)  
Data inputs and outputs are multiplexed on the same pin.  
DQ0~31  
VDD/VSS  
A9,F1,R9/  
A1,F9,R1  
(Power Supply/Ground)  
VDD and VSS are power supply pins for internal circuits.  
A7,B1,C9,D1,E9,L9,  
M1,N9,P1,R7/A3,B9,  
C1,D9,E1,L1,M9,N1,  
P9,R3  
(Power Supply/Ground)  
VDDQ and VSSQ are power supply pins for the output buffers.  
VDDQ/VSSQ  
(No Connection/Reserved for Future Use)  
This pin is recommended to be left No Connection on the device.  
F3,F7  
NC/RFU  
Feb. 2009  
www.eorex.com  
4/24  
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