eorex
Features
• Internal Double-Date-Rate architecture with 2
Accesses per clock cycle.
• 1.8V
±0.1V
VDD/VDDQ
• 1.8V LV-COMS compatible I/O
• Burst Length (B/L) of 2, 4, 8, 16
• 3 Clock read latency
• Bi-directional,intermittent data strobe(DQS)
• All inputs except data and DM are sampled
at the positive edge of the system clock.
• Data Mask (DM) for write data
• Sequential & Interleaved Burst type available
• Auto Precharge option for each burst accesses
• DQS edge-aligned with data for Read cycles
• DQS center-aligned with data for Write cycles
• No DLL ;CK to DQS is not synchronized
• Deep power down mode
• Partial Array Self-Refresh(PASR)
• Auto Temperature Compensated Self-Refresh
(TCSR) by built-in temperature sensor
• Auto Refresh and Self Refresh
• 8,192 Refresh Cycles / 64ms
EM42BM3284LBA
1Gb (8M
×
4Bank
×
32)
Double DATA RATE SDRAM
Description
The EM42BM3284LBA is Double-Date-Rate
Synchronous DRAM fabricated with ultra high
performance
CMOS
process
containing
1,073,741,824 bits which organized as 8Meg words
x 4 banks by 32 bits.
The 1Gb DDR SDRAM uses a double data rate
architecture to accomplish high-speed operation.
The data path internally pre-fetches multiple bits and
It transfers the data for both rising and falling edges
of the system clock. It means the doubled data
bandwidth can be achieved at the I/O pins.
Available packages:TFBGA-90B(13mmx11mm).
Ordering Information
Part No
EM42BM3284LBA-6F
EM42BM3284LBA-75F
Organization
32M X 32
32M X 32
Max. Freq
166MHz/DDR333 @CL3
133MHz/DDR266 @CL3
Package
TFBGA-90B
TFBGA-90B
Grade
Commercial
Commercial
Pb
Free
Free
* EOREX reserves the right to change products or specification without notice.
Feb. 2009
2/24
www.eorex.com
EOREX [ EOREX CORPORATION ]
