EN63A0QI
Table 6: Recommended REXT Resistor
output capacitors. Other capacitors with similar
characteristics may also be used. Additional bulk
capacitance from 100µF to 1000µF may be placed
beyond the voltage sensing point outside the
control loop. This additional capacitance should
have a minimum ESR of 6mΩ to ensure stable
operation. Most tantalum capacitors will have more
than 6mΩ of ESR and may be used without special
care. Adding distance in layout may help increase
the ESR between the feedback sense point and the
bulk capacitors.
VIN (V)
IMAX (µA)
REXT (kΩ)
2.5 – 4.0
4.0 – 6.6
117
88
15
51
Table 4: Recommended Output Capacitors
Description
47µF, 10V, 20%
X5R, 1206
MFG
P/N
Taiyo Yuden
LMK316BJ476ML-T
(3 capacitors needed)
47µF, 6.3V, 20%
X5R, 1206
(3 capacitors needed)
10µF, 6.3V, 10%
X7R, 0805
Murata
Taiyo Yuden
Murata
GRM31CR60J476ME19L
JMK316BJ476ML-T
GRM21BR70J106KE76L
(Optional 1 capacitor in
parallel with 3x47µF)
Taiyo Yuden
JMK212B7106KG-T
Figure 7: Selection of REXT to Connect M/S pin to VIN
Table 7: M/S (Master/Slave) Pin States
Output ripple voltage is primarily determined by the
aggregate output capacitor impedance. Placing
multiple capacitors in parallel reduces the
impedance and hence will result in lower ripple
voltage.
M/S Pin
Function
M/S pin is pulled to ground directly. This is
the Master mode. Switching PWM phase
will lock onto S_IN external clock if a signal
is available. S_OUT outputs a version of
the internal switching PWM signal.
1
1
1
1
=
+
ZTotal Z1 Z2
+...+
Low
Zn
(0V to 0.7V)
Table 5: Typical Ripple Voltages
M/S pin is left floating. Parallel operation is
not feasible. Switching PWM phase will
lock onto S_IN external clock if a signal is
available. S_OUT outputs a version of the
internal switching PWM signal.
Output Capacitor
Configuration
Typical Output Ripple (mVp-p)
Float
(1.1V to 1.4V)
3 x 47 µF
<5mV
† 20 MHz bandwidth limit measured on Evaluation Board
M/S pin is pulled to VIN with REXT. This is
the Slave mode. The S_IN signal of the
Slave should connect to the S_OUT of the
Master device. This signal synchronizes
the switching frequency and duty cycle of
the Master to the Slave device.
M/S - Ternary Pin
High
(>1.8V)
M/S is a ternary pin. This pin can assume 3 states
– A low state (0V to 0.7V), a high state (1.8V to
VIN) and a float state (1.1V to 1.4V). Device
operation is controlled by the state of the pin. The
pins may be pulled to ground or left floating without
any special care. When pulling high to VIN, a series
resistor is recommended. The resistor value may
be optimized to reduce the current drawn by the
pin. The resistance should not be too high as in that
case the pin may not recognize the high state. The
recommend resistance (REXT) value is given in the
following table.
Power-Up Sequencing
During power-up, ENABLE should not be asserted
before PVIN, and PVIN should not be asserted
before AVIN. Tying all three pins together meets
these requirements.
Technical Suport
Contact Enpirion Applications for additional support
regarding
(techsupport@enpirion.com).
the
use
of
this
product
Enpirion 2012 all rights reserved, E&OE
Enpirion Confidential
www.enpirion.com, Page 18
07077
May 9, 2012
Rev: C
ENPIRION [ ENPIRION, INC. ]
