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EN63A0QI 参数 Datasheet PDF下载

EN63A0QI图片预览
型号: EN63A0QI
PDF下载: 下载PDF文件 查看货源
内容描述: 12A同步高度集成DC-DC PowerSoC [12A Synchronous Highly Integrated DC-DC PowerSoC]
分类和应用:
文件页数/大小: 24 页 / 1511 K
品牌: ENPIRION [ ENPIRION, INC. ]
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EN63A0QI  
Design Considerations for Lead-Frame Based Modules  
Exposed Metal on Bottom of Package  
Lead-frames offer many advantages in thermal performance, in reduced electrical lead resistance, and in  
overall foot print. However, they do require some special considerations.  
In the assembly process lead frame construction requires that, for mechanical support, some of the lead-frame  
cantilevers be exposed at the point where wire-bond or internal passives are attached. This results in several  
small pads being exposed on the bottom of the package, as shown in Figure 11.  
Only the thermal pad and the perimeter pads are to be mechanically or electrically connected to the PC board.  
The PCB top layer under the EN63A0QI should be clear of any metal (copper pours, traces, or vias) except for  
the thermal pad. The “shaded-out” area in Figure 11 represents the area that should be clear of any metal on  
the top layer of the PCB. Any layer 1 metal under the shaded-out area runs the risk of undesirable shorted  
connections even if it is covered by soldermask.  
The solder stencil aperture should be smaller than the PCB ground pad. This will prevent excess solder from  
causing bridging between adjacent pins or other exposed metal under the package. Please consult the  
Enpirion Manufacturing Application Note for more details and recommendations.  
Figure 11: Lead-Frame exposed metal (Bottom View)  
Shaded area highlights exposed metal that is not to be mechanically or electrically connected to the PCB.  
Enpirion 2012 all rights reserved, E&OE  
Enpirion Confidential  
www.enpirion.com, Page 22  
07077  
May 9, 2012  
Rev: C  
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