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EN63A0QI 参数 Datasheet PDF下载

EN63A0QI图片预览
型号: EN63A0QI
PDF下载: 下载PDF文件 查看货源
内容描述: 12A同步高度集成DC-DC PowerSoC [12A Synchronous Highly Integrated DC-DC PowerSoC]
分类和应用:
文件页数/大小: 24 页 / 1511 K
品牌: ENPIRION [ ENPIRION, INC. ]
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EN63A0QI  
Table 1: Recommended RFQADJ (k) at 10A  
of the Master to the S_IN of all other Slave devices.  
Refer to Figure 5 for details.  
VOUT  
0.8V 1.2V 1.5V 1.8V 2.5V 3.3V  
Careful attention is needed in the layout for parallel  
operation. The VIN, VOUT and GND of the  
paralleled devices should have low impedance  
connections between each other. Maximize the  
amount of copper used to connect these pins and  
use as many vias as possible when using multiple  
layers. Place the Master device between all other  
Slaves and closest to the point of load.  
VIN  
3.57 3.57 4.42 4.42 3.57  
--  
3.3V 10%  
5.0V 10%  
6.0V 10%  
3.57 3.57 3.57 4.42 4.42 3.57  
3.57 3.57 3.57 4.42 4.42 3.57  
Table 2: Recommended RFQADJ (k) at 12A  
VOUT  
0.8V 1.2V 1.5V 1.8V 2.5V 3.3V  
VIN  
3.57 3.57 4.42 4.42 3.57  
--  
3.3V 10%  
5.0V 10%  
6.0V 10%  
3.57 12.1 12.1 4.42  
20.0 20.0 20.0 NR  
NR  
NR  
NR  
NR  
Note: NR = Device not rated for this operation condition  
Phase-Lock Operation:  
The EN63A0QI can be phase-locked to an external  
clock signal to synchronize its switching frequency.  
The M/S pin can be left floating or pulled to ground  
to allow the device to synchronize with an external  
clock signal using the S_IN pin. When a clock  
signal is present at S_IN, an activity detector  
recognizes the presence of the clock signal and the  
internal oscillator phase locks to the external clock.  
The external clock could be the system clock or the  
output of another EN63A0QI. The phase locked  
clock is then output at S_OUT.  
Master / Slave (Parallel) Operation and  
Frequency Synchronization  
Multiple EN63A0QI devices may be connected in a  
Master/Slave configuration to handle larger load  
currents. The device is placed in Master mode by  
pulling the M/S pin low or in Slave mode by pulling  
M/S pin high. When the M/S pin is in float state,  
parallel operation is not possible. In Master  
mode, a version of the internal switching PWM  
signal is output on the S_OUT pin. This PWM  
signal from the Master is fed to the Slave device at  
its S_IN pin. The Slave device acts like an  
extension of the power FETs in the Master and  
inherits the PWM frequency and duty cycle. The  
inductor in the Slave prevents crow-bar currents  
from Master to Slave due to timing delays. The  
Master device’s switching clock may be phase-  
locked to an external clock source or another  
EN63A0QI to move the entire parallel operation  
frequency away from sensitive frequencies. The  
feedback network for the Slave device may be left  
open. Additional Slave devices may be paralleled  
together with the Master by connecting the S_OUT  
Figure 5: Master/Slave Parallel Operation Diagram  
POK Operation  
The POK signals that the output voltage is within  
the specified range. The POK signal is asserted  
high when the rising output voltage crosses 92%  
(nominal) of the programmed output voltage. If the  
output voltage falls outside the range of 90% to  
120%, POK remains asserted for the de-glitch time  
(213µs at 1.2MHz). After the de-glitch time, POK is  
de-asserted. POK is also de-asserted if the output  
voltage exceeds 120% of the programmed output  
voltage.  
Over Current Protection  
The current limit function is achieved by sensing  
the current flowing through a sense P-FET. When  
the sensed current exceeds the current limit, both  
Enpirion 2012 all rights reserved, E&OE  
Enpirion Confidential  
www.enpirion.com, Page 15  
07077  
May 9, 2012  
Rev: C