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EN63A0QI 参数 Datasheet PDF下载

EN63A0QI图片预览
型号: EN63A0QI
PDF下载: 下载PDF文件 查看货源
内容描述: 12A同步高度集成DC-DC PowerSoC [12A Synchronous Highly Integrated DC-DC PowerSoC]
分类和应用:
文件页数/大小: 24 页 / 1511 K
品牌: ENPIRION [ ENPIRION, INC. ]
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EN63A0QI  
Application Information  
depend on the input voltage and output voltage.  
Calculate the external feedback and compensation  
network values with the equations below.  
Output Voltage Programming and loop  
Compensation  
The EN63A0QI output voltage is programmed  
using a simple resistor divider network. A phase  
lead capacitor plus a resistor are required for  
stabilizing the loop. Figure 6 shows the required  
components and the equations to calculate their  
values.  
RA [] = 48,400 x VIN [V]  
*Round RA up to closest standard value  
RB[] = (VFB x RA) / (VOUT – VFB) [V]  
VFB = 0.6V nominal  
*Round RB up to closest standard value  
The EN63A0QI output voltage is determined by the  
voltage presented at the VFB pin. This voltage is  
set by way of a resistor divider between VOUT and  
AGND with the midpoint going to VFB.  
CA [F] = 4.6 x 10-6 / RA []  
*Round CA down to closest standard value  
The EN63A0QI uses a type IV compensation  
network. Most of this network is integrated.  
However, a phase lead capacitor and a resistor are  
required in parallel with upper resistor of the  
external feedback network (Refer to Figure 6). Total  
compensation is optimized for use with three 47µF  
output capacitance and will result in a wide loop  
bandwidth and excellent load transient performance  
for most applications. Additional capacitance may  
be placed beyond the voltage sensing point outside  
the control loop. Voltage mode operation provides  
high noise immunity at light load. Furthermore,  
voltage mode control provides superior impedance  
matching to ICs processed in sub 90nm  
technologies.  
R1 = 12kΩ  
The feedback resistor network should be sensed at  
the last output capacitor close to the device. Keep  
the trace to VFB pin as short as possible.  
Whenever possible, connect RB directly to the  
AGND pin instead of going through the GND plane.  
Input Capacitor Selection  
The EN63A0QI has been optimized for use with  
two 1206 47µF input capacitors. Low ESR ceramic  
capacitors are required with X5R or X7R dielectric  
formulation.  
Y5V  
or  
equivalent  
dielectric  
formulations must not be used as these lose  
capacitance with frequency, temperature and bias  
voltage.  
In some cases modifications to the compensation  
or output capacitance may be required to optimize  
device performance such as transient response,  
ripple, or hold-up time. The EN63A0QI provides the  
capability to modify the control loop response to  
allow for customization for such applications. For  
more information, contact Enpirion Applications  
Engineering support.  
In some applications, lower value ceramic  
capacitors may be needed in parallel with the larger  
capacitors in order to provide high frequency  
decoupling. The capacitors shown in the table  
below are typical input capacitors. Other capacitors  
with similar characteristics may also be used.  
Table 3: Recommended Input Capacitors  
Description  
MFG  
P/N  
47µF, 10V, 20%  
X5R, 1206  
(2 capacitors needed)  
Murata  
GRM31CR61A476ME19L  
Taiyo Yuden  
LMK316BJ476ML-T  
Output Capacitor Selection  
The EN63A0QI has been optimized for use with  
three 1206 47µF output capacitors. Low ESR, X5R  
or X7R ceramic capacitors are recommended as  
the primary choice. Y5V or equivalent dielectric  
formulations must not be used as these lose  
capacitance with frequency, temperature and bias  
voltage.  
The  
capacitors  
shown  
Recommended Output Capacitors table are typical  
in  
the  
Figure 6: External Feedback/Compensation Network  
The feedback and compensation network values  
Enpirion 2012 all rights reserved, E&OE  
Enpirion Confidential www.enpirion.com, Page 17  
07077  
May 9, 2012  
Rev: C