ePVP6800
VFD Controller
7、Function Descriptions
7.1 Operation Registers Configuration
R PAGE Registers
Addr
R PAGE0
Indirect addressing
TCC
R PAGE1
R PAGE2
00
01
02
03
04
05
06
07
08
09
0A
0B
PC
Page, Status
RAM bank, RSR
Port5 Output data
Port6 Output data
Port7 Output data
Port8 Output data
Port9 I/O data
PLL, Main clock,WDTE
Program ROM page
Counter1 data
Counter2 LB data
Counter2 HB data
Counter3 data
Counter4 data
Counter5 data
Data RAM address
Data RAM data buffer
ADC output data buffer
Port9 pull high
0C PortC I/O data
0D Interrupt flag
PortC pull high
0E
0F
Interrupt flag, Wake-up control
Interrupt flag
10
:
1F
16 bytes
Common registers
20
:
3F
Bank0 ~ Bank3
Common registers
(32x8 for each bank)
IOC PAGE Registers
Addr
IOC PAGE0
IOC PAGE1
00
01
02
03
04
05
06
07
Port5 switch
Clock source (CN2,CN1)
Prescaler (CN2,CN1)
08
09
Clock source (CN4,CN3)
Prescaler (CN4,CN3)
Port9 I/O control
Clock source (CN5)
Prescaler (CN5)
0A
0B
0C PortC I/O control
0D Interrupt mask
0E
0F
Interrupt mask
Interrupt mask
6 of 47
11. 28.2004 (V1.23)
This specification is subject to change without further notice.
ELAN [ ELAN MICROELECTRONICS CORP ]
