ePVP6800
VFD Controller
5 Functional Block Diagram
MCU
5
4
4
4
P87 (GR1)
…
P82 (GR5)
OSCI
OSC
OSCO
P77~P76 (GR6~GR7)
…
P73~P72 (GR8~GR9)
OTP
Segment Driver/
Grid Driver/
P66~P67
(GR11/SG7~GR10/SG8)
…
High Breakdown
Driver
P62~P63 (SG5~SG6)
Data RAM
8
4
P57 (SG4/KS4)
…
P54 (SG1/KS1)
GPIO9[0:4]
GPIOC[0:4]
Timer
GPIO
PLL
IR
Real Time Clock
/RESET PLLC
VDD
VSS
VEE
Fig. 2a Block Diagram
XIN XOUT PLLC
WDT
Timer
R2
STACK
ALU
Oscillator
Timing Control
ROM
Prescaler
R1(TCC)
Interrupt
Control
Instruction
Register
R3
R5
General
RAM
Control Sleep
And Wakeup
On I/O port
Data
RAM
Instruction
Decoder
R4
Data & Control Bus
IOC5
R5
IOC6
R6
IOC7
R7
IOC8
R8
IOC9
R9
IOCC
RC
RB
Port5
(HV)
Port6
(HV)
Port7
(HV)
Port8
(HV)
Port9
PortC
Fig. 2b Block Diagram
This specification is subject to change without further notice.
11.28.2004 (V123) 3 of 47
ELAN [ ELAN MICROELECTRONICS CORP ]
