EM78P5840N/41N/42N
8-Bit Microcontrollers
Bit 1 (undefined): This bit is not used. However, it must be cleared to “0” to preclude
possible error.
Bit 2 (ADPWR): AD converter power control
"0" : disable
"1" : enable
Bit 3 ~ Bit 4 (ADCLK0 ~ ADCLK1): AD circuit‘s sampling clock source.
In Crystal mode:
ADCLK1
ADCLK0
Sampling Rate Operating Voltage
0
0
1
1
0
1
0
1
74.6K
37.4K
18.7K
9.3K
>=3.5V
>=3.0V
>=2.5V
>=2.5V
In IRC or ERIC mode:
In these modes, the AD converter rate is set by the oscillator. The
formula for the input frequency and the AD converter rate is:
Oscillator / 4
AD Converter rate =
(
2ADCLK
/12
)
For example, if input CLK = 4MHz:
ADCLK1
ADCLK0
Sampling Rate Operation Voltage
0
0
1
1
0
1
0
1
83.3K
41.7K
20.8K
10.4K
>=3.5V
>=3.0V
>=2.5V
>=2.5V
Note: The AD converter (ADC) rate must not be over 50kHz. Otherwise,
the ADC resolution will decrease.
This is a CMOS multi-channel 10-bit successive approximation of the
A/D converter. Its features are as follows:
• 74.6kHz maximum conversion speed (Crystal mode) at 5V
• Adjustable full scale input
• Internal (VDD) reference voltage
• Eight analog inputs multiplexed into one AD converter
• Power-down mode for power saving
• Complete AD conversion interrupt
• Interrupt register, AD control, and status register, and AD data register
24 •
Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
