EM78P510N
8-Bit Microcontrollers
6.2.17 Bank 1 R5 LCDCR (LCD Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LCDEN LCDTYPE
BS1
BS0
DS1
DS0
LCDF1
LCDF0
Bit 7 (LCDEN): LCD Enable Select Bit
0 : LCD disabled. All common/segment outputs are set to VDD level.
1 : LCD enabled
Bit 6 (LCDTYPE): LCD Drive Waveform Type Select Bit
0 : A type wave
1 : B type wave
Bits 5~4 (BS1~BS0): LCD Bias Select Bits
BS1
BS0
0
LCD Bias Select
1/2 Bias
0
0
1
1
1/3 Bias
X
1/4 Bias
Bits 3~2 (DS1~DS0): LCD Duty Select Bits
DS1
DS0
LCD Duty
0
0
1
1
0
1
0
1
Static
1/3 Duty
1/4 Duty
1/8 Duty
Bits 1~0 (LCDF1~LCDF0): LCD Frame Frequency Control Bits
LCD Frame Frequency (e.q. Fs=32.768K)
LCDF1 LCDF0
Static
Fs/(512×1) = 64.0 Fs/(172×3) =63.5 Fs/(128×4) = 64
Fs/(560×1) = 58.5 Fs/(188×3) = 58
Fs/(608×1) = 53.9 Fs/(204×3) = 53.5 Fs/(152×4) = 53.9 Fs/(76×8) = 53.9
Fs/(464×1) = 70.6 Fs/(156×3) = 70 Fs/(116×4) = 70.6 Fs/(58×8) = 70.6
1/3 Duty
1/4 Duty
1/8 Duty
0
0
1
1
0
1
0
1
Fs/(64×8) = 64.0
Fs/(140×4) = 58.5 Fs/(70×8) = 58.5
6.2.18 Bank 1 R6 LCDAR (LCD Address Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
LCD_A4 LCD_A3 LCD_A2 LCD_A1 LCD_A0
Bits 7~5: Reserved
Bits 4~0 (LCD_A4~LCD_A0): LCD RAM Address
Product Specification (V0.9) 09.12.2006
(This specification is subject to change without further notice)
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ELAN [ ELAN MICROELECTRONICS CORP ]
