EM78P510N
8-Bit Microcontrollers
CPU Operation Mode
Figure 6-3 CPU operation mode
6.2.14 Bank 0 RD TWTCR (TCC and WDT Timer Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WDTE
WPSR2
WPSR1
WPSR0
TCCS
TPSR2
TPSR1
TPSR0
Bit 7 (WDTE): Watchdog Timer Enable. This control bit is used to enable the watchdog
timer.
0 : Disable WDT function
1 : Enable WDT function
Bits 6~4 (WPSR2~WPSR0): WDT Prescaler Bits
WPSR2
WPSR1
WPSR0
Prescaler
1:1 (Default)
1 : 2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Bit 3 (TCCS): TCC Clock Source Select Bit
0 : Fm (main clock).
1 : Fs (sub clock: 32.768kHz)
Product Specification (V0.9) 09.12.2006
(This specification is subject to change without further notice)
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ELAN [ ELAN MICROELECTRONICS CORP ]
