EM78P510N
8-Bit Microcontrollers
6.2.10 Bank 0 R9 (Port 9)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R97
R96
R95
R94
R93
R92
R91
R90
Bits 7~0 (R97~R90): Port 9 8-bit I/O Registers.
6.2.11 Bank 0 RA (Port A)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0
Bits 7~0 (RA7~RA0): Port A 8-bit I/O Registers
6.2.12 Bank 0 RB (Port B)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
Bits 7~0 (RB7~RB0): Port B 8-bit I/O Registers
6.2.13 Bank 0 RC SCCR (System Clock Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
CLK2
CLK1
CLK0
IDLE
0
0
CPUS
Bit 7: Reserved, fixed to “0”
Bits 6~4 (CLK2~CLK0): Main Clock Select Bit for PLL Mode (code option select)
CLK2
CLK1
CLK0
Main Clock
Fs×122
Fs×61
Ex: Fs=32.768K
3.997 MHz
1.998 MHz
0.999 MHz
499.7 kHz
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
×
Fs×61/2
Fs×61/4
Fs×244
Fs×366
Fs×488
7.995 MHz
11.99 MHz
15.99 MHz
Bit 3 (IDLE): Idle Mode Enable Bit. This bit will decide SLEP instruction which mode
to go.
IDLE=”0”+SLEP instruction → sleep mode
IDLE=”1”+SLEP instruction → idle mode
Bits 2~1: Reserved, fixed to “0”
Bit 0 (CPUS): CPU Oscillator Source Select, 0/1 → sub-oscillator (fs)/ main oscillator
(fosc)When CPUS=0, the CPU oscillator select sub-oscillator and the main
oscillator is stopped.
16 •
Product Specification (V0.9) 09.12.2006
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
