EM78P510N
8-Bit Microcontrollers
6 Function Description
6.1 Register Configuration
6.1.1 R PAGE Register Configuration
Bank0
R0 ( IAR )
R1 ( TCC )
R2 ( PC )
R3 (SR)
R4 ( RSR )
RBSR
Bank1
Bank2
Bank3
Bank4
Bank5
Bank6
LCDCR
LCDAR
T1CR
TSR
URC
URS
LEDDCR
WBCR
IOC7
RPSR
URC2
LVRCR
P7ODCR
P8ODCR
P9ODCR
PAODCR
PBODCR
PORTC
PORT7
PORT8
PORT9
PORTA
PORTB
SCCR
LCDBR
T1PD
T1TD
T2CR
T2PD
T2TD
SPIS
SPIC
SPIR
SPIW
URRD
URTD
ADCR
ADICH
ADICL
ADDH
ADDL
EIESH
EIESL
P7PHCR
P8PHCR
P9PHCR
PAPHCR
PBPHCR
PCPHCR
LCDVCR
LCDCCR
LCDSCR0
LCDSCR1
LCDSCR2
IOC8
IOC9
IOCA
IOCB
IOCC
TWTCR
IMR
EIMR
EISR
ISR
WKCR
R10
‧
‧
.
.
.
.
Bank7
‧
General Purpose Ram
R20
R20
‧
‧
‧
‧
‧
‧
‧
‧
‧
‧
‧
‧
‧
‧
R3F
R3F
Figure 6-1 Data memory Configuration
6.2 Register Operations
6.2.1 R0 (Indirect Addressing Register)
R0 is not a physically implemented register. It is used as an indirect addressing pointer.
Any instruction using R0 as register actually accesses data pointed by the RAM Select
Register (R4).
6.2.2 R1 (TCC)
Incremented by the main oscillator clock (Fm) or sub oscillator clock (Fs) (controlled by
TWTCR register). Written and read by the program as any other register.
6.2.3 R2 (Program Counter)
The structure is depicted in Fig. 6-2. Generates 8K × 13 on-chip ROM addresses to the
relative programming instruction codes.
"JMP" instruction allows the direct loading of the low 10 program counter bits.
12 •
Product Specification (V0.9) 09.12.2006
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
