EM78P417N/418N/419N
8-Bit Microprocessor with OTP ROM
6.8 Dual Sets of PWM (Pulse Width Modulation)
6.8.1 Overview
In PWM mode, PWM1, PWM2, and PWM3 pins produce up to a 10-bit resolution PWM
output (see. the functional block diagram below). A PWM output consisted of a time
period and a duty cycle, and it keeps the output high. The baud rate of the PWM is the
inverse of the time period. Fig. 6-11 (PWM Output Timing) depicts the relationships
between a time period and a duty cycle.
latch
To PWM1IF
DL2H + DL2L
Fosc
DT2H
+
DT2L
1:2
1:4
1:8
Duty Cycle
Match
1:16
1:32
1:64
1:128
Comparator
MUX
PWM1
R
S
Q
1:256
TMR1H + TMR1L
reset
IOC80, 5
Comparator
T1P2 T1P1 T1P0 T1EN
Period
Match
PRD1
Data Bus
Data Bus
latch
To PWM2IF
DL2H + DL2L
DT2H
+
DT2L
Duty Cycle
Match
T2P2 T2P1 T2P0 T2EN
Comparator
PWM2
Fosc
R
S
Q
TMR2H + TMR2L
reset
1:2
1:4
1:8
MUX
1:16
IOC80, 6
1:32
Comparator
1:64
Period
Match
1:128
1:256
PRD2
latch
To PWM3IF
DL3H + DL3L
Fosc
DT3H
+
1:2
1:4
1:8
DT3L
Duty Cycle
Match
1:16
1:32
1:64
1:128
1:256
Comparator
MUX
PWM3
R
S
Q
TMR3H + TMR3L
reset
IOC80, 7
Comparator
T3P2 T3P1 T3P0 T3EN
Period
Match
PRD3
Data Bus
Data Bus
Fig. 6-10 The Three PWMs Functional Block Diagram
50 •
Product Specification (V1.0) 06.23.2005
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
