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EM78P418NP 参数 Datasheet PDF下载

EM78P418NP图片预览
型号: EM78P418NP
PDF下载: 下载PDF文件 查看货源
内容描述: 8位OTP微 [8-Bit Microprocessor with OTP ROM]
分类和应用: OTP只读存储器
文件页数/大小: 84 页 / 2325 K
品牌: ELAN [ ELAN MICROELECTRONICS CORP ]
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EM78P417N/418N/419N  
8-Bit Microprocessor with OTP ROM  
Bit 0 (ADE0 ): AD converter enable bit of P60 pin  
0 = Disable ADC0, P60 acts a s I/O pin  
1 = Enable ADC0 acts as analog input pin  
NOTE  
Note the pin priority of the COS1 and COS0 bits of IOCA0 Control register when  
P60/ADE0 acts as analog input or as digital I/O. The Comparator/OP select bits are as  
shown in a table under Section 6.2.6.  
The P60/ADE0/CO pin priority is as follows:  
P60/ADE0/CO PRIORITY  
High  
CO  
Medium  
ADE0  
Low  
P60  
6.7.1.2 R9 (ADCON: ADC Control Register)  
Bit  
7
6
CKR1  
0
5
CKR0  
0
4
3
2
ADIS2  
0
1
ADIS1  
0
0
ADIS0  
0
SYMBOL VREFS  
*Init_Value  
ADRUN ADPD  
0
0
0
*Init_Value: Initial value at power on reset  
ADCON register controls the operation of the AD conversion and decides which pin  
should be currently active.  
Bit 7(VREFS): The input source of the Vref of the ADC  
0 = The Vref of the ADC is connected to Vdd (default value), and the  
P53/VREF pin carries out the function of P53  
1 = The Vref of the ADC is connected to P53/VREF  
NOTE  
The P53/PWM3/VREF pin cannot be applied to PWM3 and VREF at the same time. IF  
P53/PWM3/VREF acts as VREF analog input pin, then PWM3E must be “0”..  
The P53/PWM3/VREF pin priority is as follows:  
P53/PWM3/VREF PIN PRIORITY  
High  
Medium  
PWM3  
Low  
P53  
VREF  
44 •  
Product Specification (V1.0) 06.23.2005  
(This specification is subject to change without further notice)  
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