EM78P417N/418N/419N
8-Bit Microprocessor with OTP ROM
6.6 Interrupt
The EM78P417/8/9N has six interrupts as listed below:
1. TCC overflow interrupt
2. Port 6 Input Status Change Interrupt
3. External interrupt [(P50, /INT) pin]
4. Analog to Digital conversion completed
5. When TMR1/TMR2/TIMER3 matches with PRD1/PRD2/PRD3 respectively in PWM
6. When the comparators output changes (for EM78P418/9N only)
Before the Port 6 Input Status Change Interrupt is enabled, reading Port 6 (e.g., "MOV
R6, R6") is necessary. Each Port 6 pin will have this feature if its status changes. Any
pin configured as output, including the P50 pin configured as /INT, is excluded from this
function. Port 6 Input Status Change Interrupt will wake up the EM78P417/8/9N from
sleep mode if it is enabled prior to going into the sleep mode by executing SLEP. When
wake-up occurs, the controller will continue to execute the succeeding program if the
global interrupt is disabled. If enabled, it will branch out to the interrupt vector 008H.
External interrupt equipped with digital noise rejection circuit (input pulse less than 8
system clocks time) is eliminated as noise. Edge selection is possible with /INT. Refer
to the Word 1 Bits 8~7 (Section 6.14.2, Code Option Register (Word 1)) for digital noise
rejection definition.
RF is the interrupt status register that records the interrupt requests in the relative
flags/bits. IOCF0 is an interrupt mask register. The global interrupt is enabled by the
ENI instruction and is disabled by the DISI instruction. When one of the interrupts
(when enabled) occurs, the next instruction will be fetched from address 008H. Once in
the interrupt service routine, the source of an interrupt can be determined by polling the
flag bits in RF. The interrupt flag bit must be cleared by instructions before leaving the
interrupt service routine to avoid recursive interrupts.
The flag (except ICIF bit) in the Interrupt Status Register (RF) is set regardless of the
status of its mask bit or of the ENI execution. Note that the result of RF will be the logic
AND of RF and IOCF0 (refer to figure below). The RETI instruction ends the interrupt
routine and enables the global interrupt (the ENI execution).
Product Specification (V1.0) 06.23.2005
• 41
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
