EM78P350N
8-Bit Microprocessor with OTP ROM
6.9.1.3 Bank 2 RA (ADOC: ADC Offset Calibration Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CALI
SIGN
VOF[2]
VOF[1]
VOF[0]
“0”
“0”
“0”
Bit 7 (CALI): Calibration enable bit for ADC offset
0 = disable Calibration
1 = enable Calibration
Bit 6 (SIGN): Polarity bit of offset voltage
0 = Negative voltage
1 = Positive voltage
Bit 5 ~ Bit 3 (VOF[2] ~ VOF[0]): Offset voltage bits
VOF[2]
VOF[1]
VOF[0]
EM78P350N
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0LSB
2LSB
4LSB
6LSB
8LSB
10LSB
12LSB
14LSB
Bit 2 ~ Bit 0: Unimplemented, read as ‘0’.
6.9.2 ADC Data Register (ADDATA/Bank 2 RB, ADDATA1H/Bank 2
RC, ADDATA1L/Bank 2 RD)
When the AD conversion is completed, the result is loaded to the ADDATA, ADDATA1H
and ADDATA1L registers. The ADRUN bit is cleared, and the ADIF is set.
6.9.3 ADC Sampling Time
The accuracy, linearity, and speed of the successive approximation of AD converter are
dependent on the properties of the ADC and the comparator. The source impedance
and the internal sampling impedance directly affect the time required to charge the
sample holding capacitor. The application program controls the length of the sample
time to meet the specified accuracy. Generally speaking, the program should wait for
2µs for each KΩ of the analog source impedance and at least 2µs for the low-impedance
source. The maximum recommended impedance for analog source is 10KΩ at Vdd=5V.
After the analog input channel is selected, this acquisition time must be done before the
conversion is started.
6.9.4 AD Conversion Time
CKR1 and CKR0 select the conversion time (Tct), in terms of instruction cycles. This
allows the MCU to run at a maximum frequency without sacrificing the AD conversion
accuracy. For the EM78P350N, the conversion time per bit is 4µs.
68 •
Product Specification (V1.0) 09.14.2006
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
