EM78P350N
8-Bit Microprocessor with OTP ROM
External interrupt with digital noise rejection circuit (input pulse less than 8 system clock
cycle) is eliminated as noise. Edge selection is possible with /INT. Refer to Word 1 Bits
8~7 (Section 6.16.2, Code Option Register (Word 1)) for digital noise rejection definition.
RF is the interrupt status register that records the interrupt requests in the relative
flags/bits. IOCF is an interrupt mask register. The global interrupt is enabled by the
ENI instruction and is disabled by the DISI instruction. When one of the interrupts
(when enabled) occurs, the next instruction will be fetched from address 008H. Once in
the interrupt service routine, the source of an interrupt can be determined by polling the
flag bits in RF. The interrupt flag bit must be cleared by instructions before leaving the
interrupt service routine to avoid recursive interrupts.
The flag (except ICIF bit) in the Interrupt Status Register (RF) is set regardless of the
status of its mask bit or of the ENI execution. Note that the result of RF will be the logic
AND of RF and IOCF (refer to the figure below). The RETI instruction ends the
interrupt routine and enables the global interrupt (the ENI execution).
Fig. 6-8 Interrupt Input Circuit
64 •
Product Specification (V1.0) 09.14.2006
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
