EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.4 I/O Ports
The I/O registers (Port 5, Port 6, and Port 7) are bidirectional tri-state I/O ports. Port 5
is pulled-high and pulled-down internally by software. Likewise, P6 has its open-drain
output set through software. Port 5 features an input status changed interrupt (or
wake-up) function. Each I/O pin can be defined as "input" or "output" pin by the I/O
control register (IOC5 ~ IOC7). The I/O registers and I/O control registers are both
readable and writable. The I/O interface circuits for Port 5, Port 6, and Port 7 are
illustrated in Figures 6-4, 6-5, 6-6, & 6-7 (see next page).
PCRD
P
Q
D
R
PCWR
CLK
_
Q
C
L
P
IOD
PORT
Q
D
R
PDWR
CLK
_
Q
C
L
PDRD
0
1
M
U
X
Note: Open-drain is not shown in the figure.
Fig. 6-4 I/O Port and I/O Control Register Circuit for Port 6 and Port 7
PCRD
P
Q
_
D
R
PCWR
PDWR
CLK
Q C
L
IOD
P
Q
PORT
D
R
_
CLK
Q C
Bit 6 of IOCE
L
P
D
Q
R
0
1
M
U
X
_
Q
CLK
C
L
PDRD
INT
Note: Open-drain is not shown in the figure.
Fig. 6-5 I/O Port and I/O Control Register Circuit for P60 (/INT)
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
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ELAN [ ELAN MICROELECTRONICS CORP ]
