EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
NOTE
The internal TCC will stop running when in sleep mode. However, during AD
conversion, when TCC is set to “SLEP” instruction, if the ADWE bit of the RE register is
enabled, TCC will keep on running.
The watchdog timer is a free running on-chip RC oscillator. The WDT will keep on
running even when the oscillator driver has been turned off (i.e., in sleep mode).
During normal operation or in sleep mode, a WDT time-out (if enabled) will cause the
device to reset. The WDT can be enabled or disabled any time during normal mode
through software programming. Refer to WDTE bit of IOCE0 register (Section 6.2.10
IOCE0 (WDT Control & Interrupt Mask Registers 2). With no prescaler, the WDT
time-out period is approximately 18ms1 or 4.5ms2.
CLK (Fosc/2 or Fosc/4)
Data Bus
0
8-Bit Counter (IOCC1)
MUX
SYNC
2 cycles
TCC (R1)
TCC Pin
1
8 to 1 MUX
Prescaler
TE (CONT)
TCC overflow
interrupt
TS (CONT)
PSR2~0
(CONT)
WDT
8-Bit Counter
8 to 1 MUX
Prescaler
WDTE
(IOCE0)
PSW2~0
(IOCE0)
WDT Time out
Fig. 6-3 TCC and WDT Block Diagram
1
2
VDD=5V, WDT time-out period = 16.5ms ± 30%
VDD=3V, WDT time-out period = 18ms ± 30%
VDD=5V, WDT time-out period = 4.2ms ± 30%
VDD=3V, WDT time-out period = 4.5ms ± 30%
32 •
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
