EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.2.21 IOCE1 (Output Sink Select Control Register)
Bit
EM78P342N/343N
ICE342N
7
6
5
4
3
2
1
0
-
TIMERSC CPUS
IDLE
IDLE
HS3
HS3
HS2
HS2
HS1
HS1
HS0
HS0
WDTPS TIMERSC CPUS
Bit 7 (WDTPS):
WDT time-out period selection bit.
0 : 4.5ms
1 : 18ms
Bit 6 (TIMERSC): TCC, TCCA, TCCB, TCCC clock sources select 0/1 → Fs/Fm*
Fs: sub frequency for WDT internal RC time base
Fm: main-oscillator clock
Bit 5 (CPUS):
CPU Oscillator Source Select, 0/1 → sub-oscillator (fs) / main
oscillator (fosc)
When CPUS=0, the CPU oscillator select sub-oscillator and the
main oscillator is stopped.
Bit 4 (IDLE):
Idle Mode Enable Bit. This bit will decide SLEP instruction which
mode to go.
0 : Idle=”0”+SLEP instruction → sleep mode
1 : Idle=”1”+SLEP instruction → idle mode
CPU Operation Mode
Code
option
HLFS=1
RESET
Normal Mode
fosc:oscillation
fs: oscillation
external
interrupt
CPU: using fosc
wake up
CPUS="0"
CPUS="1"
IDLE="0"
+SLEP
IDLE="1
"+SLEP
IDLE="1
"+SLEP
external
interrupt
SLEEP Mode
Green Mode
fosc:stop
IDLE Mode
fosc:stop
fs: stop
fosc:stop
fs: oscillation
fs: oscillation
IDLE="0"
SLEP
CPU: stop
CPU: using fs
CPU: stop
wake up
Fig. 6-2 CPU Operation Mode
Bit 3 (HS3):
Bit 2 (HS2):
Output Sink current Select for P63
(Not applicable for EM78P341N)
Output Sink current Select for P62.
(Not applicable for EM78P341N)
Bit 1 (HS1):
Bit 0 (HS0):
Output Sink current Select for P61.
Output Sink current Select for P60.
HSx
0
VDD = 5V, Sink Current
20mA (in 0.3VDD)
1
90mA (in 0.3VDD)
30 •
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
