EM78P257
OTP ROM
enabled) will cause the device to reset. The WDT can be enabled or disabled at any time during the normal mode
by software programming. Refer to WDTE bit of IOCE0 register. With no prescaler, the WDT time-out period is
approximately 18 ms1 or 1ms2 (one oscillator start-up timer period).
CLK (Fosc/2 or Fosc/4)
Data Bus
0
1
8-Bit Counter (RC)
MUX
SYNC
2 cycles
TCC Pin
TCC (R1)
8 to 1 MUX
Prescaler
TE (CONT)
TCC overflow
interrupt
TS (CONT)
PSR2~0
(CONT)
WDT
8-Bit counter
8 to 1 MUX
Prescaler
WDTE
(IOCE0)
PSW2~0
(IOCE0)
WDT Time out
Fig. 6 Block Diagram of TCC and WDT
4.4 I/O Ports
The I/O registers, (Port 5, Port 6, and Port 7), are bi-directional tri-state I/O ports. Port 5 is pulled-high internally by
software. Likewise, P6 has its open-drain output also through software. Port 5 features an input status changed
interrupt (or wake-up) function and is pulled-down by software. Each I/O pin can be defined as "input" or "output" pin
by the I/O control register (IOC5 ~ IOC7). The I/O registers and I/O control registers are both readable and writable.
The I/O interface circuits for Port 5, Port 6 and Port7 are shown in Fig. 7, Fig. 8, and Fig. 9 respectively.
1 NOTE: VDD=5V, Setup time period = 15.4ms ± 30%.
VDD=3V, Setup time period = 17.6ms ± 30%.
2 NOTE: VDD=5V, Setup time period = 1.07ms ± 30%.
VDD=3V, Setup time period = 1.22ms ± 30%.
This specification is subject to change without prior notice.
29
07.27.2004 (V1.4)
ELAN [ ELAN MICROELECTRONICS CORP ]
