EM78P257
OTP ROM
15. IOC81 (TCCC Counter )
An eight-bit clock counter. It can be read, written and cleared on any reset condition. When in
Mouse-Mode, it is Up/Down Counter, else it is UP Counter.
16. IOC91 ( Low-time Register )
The 8-bit Low-time register controls the active or Low period of the pulse.
The decimal value of its contents determines the number of oscillator cycles and verifies that the IR
OUT pin is active. The active period of IR OUT can be calculated as follows:
tLow=(decimal value held in Low-time register)/fosc
17. IOCA1 ( High-time Register )
The 8-bit High-time register controls the inactive or High period of the pulse.
The decimal value of its contents determines the number of oscillator cycles and verifies that the IR
OUT pin is inactive. The inactive period of IR OUT can be calculated as follows:
tHigh=(decimal value held in High-time register)/fosc
18. IOCB1 ( Pulse timer Register )
The contents of the Low-time and High-time register are loaded alternately into the Pulse timer.
When loaded, the contents of Pulse timer are decremented on every oscillator cycle. Upon reaching
zero, the Pulse timer will be loaded with the contents of the other.
4.3 TCC/WDT & Prescaler
There are two 8-bit counters available as prescalers for the TCC and WDT respectively. The PSR0~PSR2 bits of the
CONT register are used to determine the ratio of the prescaler of TCC. Likewise, the PWR0~PWR2 bits of the
IOCE0 register are used to determine the prescaler of WDT. The prescaler (PSR0~PSR2) will be cleared by the
instructions each time they are written into TCC. The WDT and prescaler will be cleared by the “WDTC” and “SLEP”
instructions. Fig.6 depicts the circuit diagram of TCC/WDT.
• R1(TCC) is an 8-bit timer/counter. The clock source of TCC can be internal clock or external singal input (edge
selectable from the TCC pin). If TCC signal source is from internal clock, TCC will increase by 1 at every instruction
cycle (without prescaler). As illustrated in Fig. 6, selection of CLK=Fosc/2 or CLK=Fosc/4 depends on the CODE
Option bit <CLKS>. CLK=Fosc/2 is selected if the CLKS bit is "0", and CLK=Fosc/4 is selected if the CLKS bit is
"1". If TCC signal source is from external clock input, TCC will increase by 1 at every falling edge or rising edge of
the TCC pin.
• The watchdog timer is a free running on-chip RC oscillator. The WDT will keep on running even after the oscillator
driver has been turned off (i.e. in sleep mode). During the normal operation or the sleep mode, a WDT time-out (if
This specification is subject to change without prior notice.
28
07.27.2004 (V1.4)
ELAN [ ELAN MICROELECTRONICS CORP ]
