EM78P257
OTP ROM
• Bit 0 (/PH50) Use to enable the pull-high of P50 pin.
• IOCD0 Register is both readable and writable.
10. IOCE0 (WDT Control Register)
7
6
5
-
4
-
3
-
2
1
0
WDTE
EIS
PSW2
PSW1
PSW0
• Bit 7 (WDTE) Control bit is used to enable Watchdog timer.
0: Disable WDT.
1: Enable WDT.
WDTE is both readable and writable.
• Bit 6 (EIS) Control bit is used to define the function of P60(/INT) pin.
0: P60, bi-directional I/O pin.
1: /INT, external interrupt pin. In this case, the I/O control bit of P60 (bit 0 of IOC6) must be set to "1".
When EIS is "0", the path of /INT is masked. When EIS is "1", the status of /INT pin can also be read
by way of reading Port 6 (R6). Refer to Fig. 8.
EIS is both readable and writable.
• Bit5~3 Not used.
• Bit 2 (PSW2) ~ Bit 0 (PSW0) WDT prescaler bits.
PSW2
PSW1
PSW0
WDT Rate
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
11. IOCF0 (Interrupt Mask Register)
7
6
5
4
3
2
1
0
CMP4IE
CMP3IE
CMP2IE
CMP1IE PPC/CMP
EXIE
ICIE
TCIE
• Bit 7 (CMP4IE) CMP3IF interrupt enable bit.
0: disable CMP4IF interrupt
1: enable CMP4IF interrupt
• Bit 6 (CMP3IE) CMP3IF interrupt enable bit.
0: disable CMP3IF interrupt
1: enable CMP3IF interrupt
• Bit 5 (CMP2IE) CMP2IF interrupt enable bit.
This specification is subject to change without prior notice.
26
07.27.2004 (V1.4)
ELAN [ ELAN MICROELECTRONICS CORP ]
