EM78P257
OTP ROM
0: disable CMP2IF interrupt
1: enable CMP2IF interrupt
• Bit 4 (CMP1IE) CMP1IF interrupt enable bit.
0: disable CMP1IF interrupt
1: enable CMP1IF interrupt
• Bit 3 (CMP/PPC) Wake-up by which Interrupt sources.
0: PPC, wake-up by Port 5 input status change. (if enabled)
1: CMP, wake-up by comparators status change. (if enabled)
• Bit 2 (EXIE) EXIF interrupt enable bit.
0: disable EXIF interrupt
1: enable EXIF interrupt
• Bit 1 (ICIE) ICIF interrupt enable bit.
0: disable ICIF interrupt
1: enable ICIF interrupt
• Bit 0 (TCIE) TCIF interrupt enable bit.
0: disable TCIF interrupt
1: enable TCIF interrupt
• Individual interrupt is enabled by setting its associated control bit in the IOCF0 to "1".
• Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. Refer to Fig.
10.
• IOCF0 register is both readable and writable.
12. IOC51 ( TCCA Counter )
An eight-bit clock counter. It can be read, written and cleared on any reset condition. When in
Mouse-Mode, it is Up/Down Counter, else it is UP Counter.
13. IOC61 ( TCCBL Counter) /LSB Counter
An eight-bit clock counter is for the least significant byte of TCCBX. TCCBL. It can be read, written
and cleared on any reset condition. When in Mouse-Mode, it is Up/Down Counter; When in IR-Mode,
it is Down Counter, else it is Up Counter.
14. IOC71 (TCCBH Counter) /MSB Counter
An eight-bit clock counter is for the most significant byte of TCCBX. TCCBH. It can be read, written
and cleared on any reset condition. When TCCBE(IOC80) is “0” THEN TCCBH is disable, TCCBE
is”1” then TCCB is 16 bit length counter. When it is in IR-Mode, it is Down Counter, else it is UP
Counter.
This specification is subject to change without prior notice.
27
07.27.2004 (V1.4)
ELAN [ ELAN MICROELECTRONICS CORP ]
