EM78P257
OTP ROM
• Bit 3 Not used
• Bit 2(TCCCIE) TCCCIF interrupt enable bit.
0: disable the TCCCIF interrupt
1: enable the TCCCIF interrupt
• Bit 1(TCCCTS) TCCC signal source
0: internal instruction cycle clock
1: transition on the TCC5 pin.
• Bit 0(TCCCTE) TCCC signal edge
0: increment if the transition from low to high (leading edge) takes place on the TCC6 pin
1: increment if the transition from high to low (leading edge) takes place on the TCC6 pin
Table 25 MOUSE Control Register
7
6
-
5
-
4
-
3
-
2
-
1
-
0
-
MOUSEN
• Bit 7 (MOUSEN) Mouse application Enable bit.
0: Disable MOUSEN. TCCA,TCCB and TCCC are increment counters.
1: Enable MOUSEN. RA(disable Bit0(TCCATE), Bit1(TCCATS) is ‘ 1’ , Bit2(TCCAIE) is ‘ 0’ ),
RB(disable Bit0(TCCCTE), Bit1(TCCCTS) is ‘ 1’ , Bit2(TCCCIE) is ‘ 0’ , Bi, disable Bit4(TCCBTE),
Bit5(TCCBTS) is ‘ 1’ , Bit6(TCCBIE) is ‘ 0’ ) , and TCCA, TCCBL and TCCC work as up/down counters.
For other pin assignments, refer to IOC80.
• Bit 6~Bit 0 Not used.
4. MOUSE mode Timing
(1)Photo-couples pulse width:
X1(Y1)
X2(Y2)
Tr
Tf
Counter increment if the rising/falling edge of X1 is leading the one on X2.
Counter decrement if the rising/falling edge of X1 is falling behind the one on X2.
(2) Sending DATA (data from EM78P257A/B to system)
This specification is subject to change without prior notice.
56
07.27.2004 (V1.4)
ELAN [ ELAN MICROELECTRONICS CORP ]
