EM78815
8-Bit Microcontroller
Bit 0 ~ Bit 2 (SBR0 ~ SBR2) : SPI baud rate selection bits
SBR2
SBR1
SBR0
Mode
Master
Master
Master
Master
Master
Master
Slave
Baud Rate
Fsco
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Fsco/2
Fsco/4
Fsco/8
Fsco/16
Fsco/32
×
Note: Fsco = CPU Instruction Clock
Example:
If PLL enable and RA Page 0 (Bit 5, Bit 4) = (1, 1), instruction clock is 3.58 MHz/2 →
Fsco=3.5862MHz/2
If PLL enable and RA Page 0 (Bit 5, Bit 4) = (0, 0), instruction clock is 0.895 MHz/2 →
Fsco=0.895 MHz/2
If PLL disable, instruction clock is 32.768kHz/2 → Fsco=32.768kHz/2.
Bit 3 (SCES) : SPI clock edge selection bit
0 → Data shifts out on a rising edge, and shifts in on falling edge.
Data is hold during the low level.
1 → Data shifts out on falling edge, and shifts in on rising edge. Data
is hold during the high level.
Bit 4 (SE) :
SPI shift enable bit
0 → Reset as soon as the shifting is complete, and the next byte is
ready to shift.
1 → Start to shift, and remain a 1 while the current byte is still being
transmitted.
NOTE
This bit has to be reset by software.
Product Specification (V2.4) 08.01.2004
(This specification is subject to change without further notice)
25
ELAN [ ELAN MICROELECTRONICS CORP ]
