EM78815
8-Bit Microcontroller
Bit 5 (SRO) : SPI read overflow bit
0 → No overflow
1 → A new data is received while the previous data is still being hold
in the SPIB register. In this situation, the data in SPIS register will
be destroyed. To avoid setting this bit, users have to read the
SPIB register even if only the transmission is implemented. Note
that this can only occur in slave mode.
Bit 6 (SPIE) : SPI enable bit
0 → Disable SPI mode
1 → Enable SPI mode
Bit 7 (RBF) : SPI read buffer full flag
0 → Receive is not finished yet, SPIB is empty.
1 → Receive is finished, SPIB is full.
Write
R5
Read
R5
RBF
set to 1
Buffer Full Detector
RBFI
SPIWC
SPIR reg.
SPIW reg.
SPIE
SDI
shift right
SDI/P62
SPIS reg.
MUX
PORT62
bit 0
bit 7
SDO
SPIC reg. (R4 page1)
SDO/P61
MUX
PORT61
Edge
Select
SPIE
0
3
Noise
Filter
SBR2~SBR0
SBR0 ~SBR2
2
3
Clock Select
Tsco
Prescaler
4, 8, 16, 32, 64, 128
SCK
Edge
Select
SCK/P60
MUX
PORT60
16.38kHz
SCK
SPIE
Fig. 13 SPI Structure
26 •
Product Specification (V2.4) 02.17.2006
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
