EM78808
8-bit Micro-controller
Bit 3(INT0) : External INT0 pin interrupt flag
If PORT70 ,PORT71,PORT72 or PORT73 has a falling edge trigger signal. CPU will set this bit.
Bit 4(INT1) : External INT1 pin interrupt flag
If PORT74 ,PORT75 or PORT76 has a falling edge trigger signal. CPU will set this bit.
Bit 5(INT2) : External INT2 pin interrupt flag
If PORT77 has a falling edge or rising edge (controlled by CONT register) trigger signal. CPU will set this
bit.
Bit 6(FSK/CW) : FSK data or Call waiting data interrupt flag.
If FSKDATA or CAS has a falling edge trigger signal, CPU will set this bit.
Bit 7( RBF/STD) : SPI data transfer complete or DTMF receiver signal valid interrupt
If serial IO 's RBF signal has a rising edge signal (RBF set to "1" when transfer data completely), CPU will
set this bit. Or DTMF receiver's STD signal has a rising edge signal (DTMF decode a DTMF signal).
IOCF is the interrupt mask register. User can read and clear.
Trigger edge as the table
Signal
Trigger
<Note>
TCC
Time out
Time out
Time out
Falling edge
Falling edge
COUNTER1
COUNTER2
INT0
INT1
INT2
Falling/Falling & rising edge Controlled by CONT register
FSK
RBF/STD
Falling edge
Rising edge
R10~R3F (General Purpose Register)
R10~R3F (Banks 0 ~ 3) : All of them are general purpose registers.
VII.2 Special Purpose Registers
A (Accumulator)
Internal data transfer, or instruction operand holding
It's not an addressable register.
CONT (Control Register)
7
6
INT
5
TS
4
-
3
PAB
2
1
0
INT_EDGE
PSR2
PSR1
PSR0
Bit 0~Bit 2(PSR0~PSR2) : TCC/WDT prescaler bits
PSR2
PSR1
PSR0
TCC rate
1:2
WDT rate
1:1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:4
1:8
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:16
1:32
1:64
1:128
1:256
Bit 3(PAB) : Prescaler assignment bit
0/1 ꢂTCC/WDT
Bit 4 : undefined
Bit 5(TS) : TCC signal source
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* This specification is subject to change without notice.
8/1/2004 (V3.1)
29
ELAN [ ELAN MICROELECTRONICS CORP ]
