EM78808
8-bit Micro-controller
0 ꢂInstruction clock
1 ꢂ16.384kHz
Instruction clock = MCU clock/2, Refer to RA Bit 4 ~ Bit 6 for PLL and Main clock selection. See fg.17.
Bit 6(INT) : INT enable flag
0 ꢂinterrupt masked by DISI or hardware interrupt
1 ꢂinterrupt enabled by ENI/RETI instructions
Bit 7(INT_EDGE) : interrupt edge type of P77
0 ꢂ77 's interruption source is a rising edge signal and falling edge signal.
1 ꢂP77 's interruption source is a falling edge signal.
CONT register is readable (CONTR) and writable (CONTW).
TCC and WDT :
There is an 8-bit counter available as prescaler for the TCC or WDT. The prescaler is available for the TCC
only or WDT only at the same time.
An 8 bit counter is available for TCC or WDT determined by the status of the bit 3 (PAB) of the CONT
register.
See the prescaler ratio in CONT register.
Fig.16 depicts the circuit diagram of TCC/WDT.
Both TCC and prescaler will be cleared by instructions which write to TCC each time.
The prescaler will be cleared by the WDTC and SLEP instructions, when assigned to WDT mode.
The prescaler will not be cleared by SLEP instructions, when assigned to TCC mode.
Data
Bus
Instruction clock
M
M
U
X
U
X
SYNC
2 cycles
16.384kHz
TCC(R1)
TS
TCC overflow interrupt
PAB
M
U
X
8-bit Counter
WDT
PSR0 ~
PSR2
8-to-1 MUX
MUX
WDTE
PAB
PAB
WDT timeout
Fig.17 Block diagram of TCC WDT
IOC5 (PORT5 I/O control, PORT switch, Key tone, CDAS, LCD bias)
PAGE0 (PORT5 I/O control register, PORT switch)
7
6
5
4
3
2
1
0
CASPWR
P9SH
P9SL
P8SH
P8SL
IOC57
IOC56
IOC55
Bit 0 (P8SL) : Switch low nibble I/O PORT8 or LCD segment output for share pins SEGxx/P8x pins
0 ꢂselect normal P80 ~ P83 for low nibble PORT8
1 ꢂselect SEG64 ~ SEG67 output for LCD SEGMENT output.
Bit 1 (P8SH) : Switch high nibble I/O PORT8 or LCD segment output for share pins SEGxx/P8x pins
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* This specification is subject to change without notice.
8/1/2004 (V3.1)
30
ELAN [ ELAN MICROELECTRONICS CORP ]
