EM78808
8-bit Micro-controller
PAGE1 (Data RAM address0 ~ address7)
7
6
5
4
3
2
1
0
RAMA7
RAMA6
RAMA5
RAMA4
RAMA3
RAMA2
RAMA1
RAMA0
Bit 0~Bit 7(RAMA0~RAMA7) : Data RAM address (address0 to address7) for RAM reading or writing
RE (CAS, Key scan, LCD control, Data RAM address(8 ~ 10))
PAGE0 (Key scan control, LCD control)
7
6
5
4
3
2
1
0
CAS
KEYCHK KEYSTRB KEYSCAN
LCD1
LCD0
LCDM1
LCDM0
Bit 0~Bit 1(LCDM0~LCDM1) : LCD common mode, bias select and COM/SEG switch control bits
LCDM1, LCDM0
COM output mode LCD bias
COM/SEG switch
0,0
0,1
1,0
1,1
16 common
9 common
8 common
24 common
1/4 bias
1/4 bias
1/4 bias
1/5 bias
SEG0 ~ SEG7 select
SEG0 ~ SEG7 select
SEG0 ~ SEG7 select
COM16 ~ COM23 select
<Note> When 8, 9 and 16 LCD common mode is set, COM16/SEG0 pin ~ COM23/SEG7 pin are also set to
SEG0 ~ SEG7 and LCD bias is 1/4 bias. When 24 LCD common mode is set, COM16/SEG0 pin ~
COM23/SEG7 pin are also set to COM16 ~ COM23 and LCD bias is 1/5 bias.
Bit 2~Bit 3 (LCD0~LCD1) : LCD operation function definition.
LCD1, LCD0
LCD operation
Disable
Blanking
Reserved
LCD enable
0,0
0,1
1,0
1,1
<Note> Key strobe and Key check functions should be normal operating whenever LCD is enabled or disabled.
The controller can drive LCD directly. LCD block is made up of LCD driver, display RAM, segment
output pins, common output pins and LCD operating bias pins.
Duty, the number of segment , the number of common and frame frequency are determined by LCD mode
register RE PAGE0 Bit 0~ Bit 1.
When 8, 9 or 16 LCD commons are used, LCD operating bias pins VC1, VC2, VC4 and VC5 need to be
connected 0.1uF capacitors to the ground (VC3 is not necessary). When 24 LCD common is used, all LCD
operating bias pins VC1 ~ VC5 need to be connected 0.1uF capacitors to the ground.
LCD driver can be controlled as different driving ability (refer to IOC6 PAGE1 Option-B register).
The basic structure contains a timing control which uses the basic frequency 32.768kHz to generate the proper
timing for different duty and display access. RE PAGE1 register is a command register for LCD driver and
display. The LCD display (disable, enable, blanking) is controlled by RE PAGE0 Bit 2 ~ Bit 3 and the driving
duty is decided by RE PAGE Bit 0 ~ Bit 2. LCD display data is stored in data RAM which address and data
access controlled by registers R9, RA PAGE1 and RB PAGE1.
User can regulate the contrast of LCD display by IOC5 PAGE1 (BIAS3..BIAS0). Up to 16 levels contrast is
convenient for better display. And the internal voltage follower can afford large driving source.
COM signal : The number of COM pins varies according to the duty cycle used, as following:
In 1/8 duty mode COM8 ~ COM15 must be open.
In 1/9 duty mode COM9~ COM15 must be open
In 1/16 duty mode COM0 ~ COM15 pins must be used.
In 1/24 duty mode COM0 ~ COM23 pins must be used.
______________________________________________________________________________________________________________________________________________________
* This specification is subject to change without notice.
8/1/2004 (V3.1)
25
ELAN [ ELAN MICROELECTRONICS CORP ]
