EM78808
8-bit Micro-controller
Bit 6 (PLLEN) : PLL enable control bit
It is CPU mode control register. If PLL is enabled, CPU will operate at normal mode (high frequency,
main clock); otherwise, it will run at green mode (low frequency, 32768 Hz).
0/1 ꢂdisable/enable
3.5826MHz to analog circuit
÷ 4
=>895.658kHz
=>1.7913MHz
=>3.5826MHz
=>10.7479MHz
2
÷
PLL
× 1
× 3
1
switch
System clock
Sub-clock
ENPLL
0
32.768kHz
CLK1 ~ CLK0
Fig.10 The relation between 32.768kHz and PLL
Bit 7: Unused register. Always keep this bit to 0 or some un-expect error will happen!
The status after wake-up and the wake-up sources list as the table below.
Wakeup signal
SLEEP mode
GREEN mode
NORMAL mode
RA(7,6)=(0,0) RA(7,6)=(x,0)
RA(7,6)=(x,1)
no SLEP
Interrupt
+ SLEP
no SLEP
Interrupt
TCC time out
IOCF bit 0=1
And "ENI"
No function
(jump to address 8 (jump to address
at page0)
Interrupt
8 at page0)
Interrupt
COUNTER1 time out No function
IOCF bit 1=1
(jump to address 8 (jump to address
And "ENI"
COUNTER2 time out No function
IOCF bit 2=1
And "ENI"
WDT time out
at page0)
Interrupt
(jump to address 8 (jump to address
at page0) 8 at page0)
RESET and Jump RESET and
8 at page0)
Interrupt
RESET and
Jump to address to address 0
0
Jump to address
0
PORT7
RESET and
Interrupt
Interrupt
IOCF bit3 or bit4 or
bit5 = 1
Jump to address (jump to address 8 (jump to address
0
at page0)
8 at page0)
And "ENI"
DED interrupt
No function
Interrupt
Interrupt
IOCE page2 bit 6 = 1
And RE page1 bit6
logic level variation
(switch by EDGE bit)
And “ENI”
(jump to address 8 (jump to address
at page0)
8 at page0)
Stack overflow
IOC5 page2 bit7=1
&bit 6: 0ꢂ1
No function
Interrupt
Interrupt
(jump to address 8 (jump to address
at page0) 8 at page0)
And “ENI”
<Note> Stack overflow interrupt function is exist in ROM less and OTP chip only.
<Note> PORT70 ~ PORT73 's wakeup function is controlled by IOCF bit3 and ENI instruction. They are
falling edge trigger.
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* This specification is subject to change without notice.
8/1/2004 (V3.1)
21
ELAN [ ELAN MICROELECTRONICS CORP ]
