EM78808
8-bit Micro-controller
R9 (PORT9 I/O data, extra LCD address bit, Data ROM address(16~17) )
PAGE0 (PORT9 I/O data register)
7
6
5
4
3
2
1
0
P97
P96
P95
P94
P93
P92
P91
P90
Bit 0 ~ Bit 7 (P90 ~ P97) : 8-bit PORT9 ( 0~7 ) I/O data register
User can use IOC register to define input or output each bit.
PAGE1 (LCD address MSB bit, Data ROM address bits)
7
6
5
4
3
2
1
0
LCDA8
DROM_A17 DROM_A16
Bit 0 ~ Bit 1 (DROM_A16 ~ DROM_A17) : Data ROM address(16~17) for ROM reading.
Bit 2 ~ Bit 6 : unused
Bit 7 (LCDA8) : MSB of LCD address for LCD RAM reading or writing
Other LCD address bits LCDA7 ~ LCDA0 are set from RA PAGE1 Bit 7 ~ Bit 0.
For LCD address access over 0xFFH, set this bit to “1”; otherwise set this bit to “0”.
RA (CPU power saving, PLL, Main clock selection, FSK, Watchdog timer, LCD
address)
PAGE0 (CPU power saving bit, PLL, Main clock selection bits, FSK , Watchdog timer
enable bit)
7
6
5
4
3
2
1
0
0
PLLEN
CLK1
CLK0
FSKPWR FSKDATA
/CD
WDTEN
Bit 0 (WDTEN) : Watch dog control register
User can use WDTC instruction to clear watch dog counter. The counter 's clock source is 32768/2 Hz. If
the prescaler assigns to TCC. Watch dog will time out by (1/32768 )*2 * 256 = 15.616ms. If the prescaler
assigns to WDT, the time of time out will be more times depending on the ratio of prescaler.
0/1 ꢂdisable/enable
Bit 1 (/CD) : FSK carrier detect indication
0/1 ꢂCarrier Valid/Carrier Invalid
It's a read only signal. If FSK decoder detect the energy of mark or space signal. The Carrier signal will go
to low level. Otherwise it will go to high.. Note!! Should be at normal mode.
Bit 2 (FSKDATA) : FSK decoding data output
It's a read only signal. If FSK decode the mark or space signal , it will output high level signal or low level
signal at this register. It's a raw data type. That means the decoder just decode the signal and has no process
on FSK signal. Note!! Should be at normal mode.
User can use FSK data falling edge interrupt function to help data decoding.
Ex:
MOV
IOW
CLR
ENI
:
A,@01000000
IOCF
RF
;enable FSK interrupt function
;wait for FSK data's falling edge
0 = Space data ( 2200Hz )
1 = Mark data (1200Hz)
Bit 3 (FSKPWR) : FSK power control
0/1 ꢂFSK decoder powered down / FSK decoder powered up
It's the control register of FSK block power.
The relation between bit 1 to bit 3 is shown in Fig.9. You have to power FSK decoder up first, then wait a
setup time (Tsup) and check carrier signal (/CD). If the carrier is low, program can process the FSK data.
______________________________________________________________________________________________________________________________________________________
* This specification is subject to change without notice.
8/1/2004 (V3.1)
19
ELAN [ ELAN MICROELECTRONICS CORP ]
