EM77950
BB Controller
8.3.7 System Control Register 3 (SCR3)
This register is a read and a write register.
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ZERO
DISCH
CNT 2
ZERO
DISCH
CNT 1
ZERO
DISCH
CNT 0
EN
ZERO
DISCH.
LOW
MODE
CAP DIS EN CAP
PERIOD DISCH.
SCR3
-
Bit 1: EN_CAP_DISCH
Enables/disables capacitor discharge mechanism after each received packet:
0: Disables discharge.
1: Enables discharge.
This bit overrides Bit 3.
Bit 2: CAP_DIS_PERIOD
Determines the capacitor discharge duration:
0: The pulse width is 36 clocks, (3 μsec at 12 MHz clock).
1: The pulse width is 72 clocks, (3 μsec at 24 MHz clock).
Bit 3: EN_ZERO_DISCH
Enables/disables zero counter mechanism for capacitor discharge:
0: Disables discharge
1: Enables discharge
Bits 4-6: ZERO_DISCH_CNT [0:2]
Determine the number of zero bits that will trigger a capacitor discharge by the
zero counter mechanism.
ZERO DISCH
CNT 0
ZERO DISCH
CNT 1
ZERO DISCH
CNT 2
Number of Zeros
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
5
10
15
20
25
30
35
40
Product Specification (V1.0) 10.09.2007
(This specification is subject to change without further notice)
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ELAN [ ELAN MICROELECTRONICS CORP ]
