EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
7.2.2 Writing Data to Display RAM Data
The EM65101 is a 128-row by 160-column addressable array. Each pixel can be
accessed when the X and Y addresses are specified. The 128 rows are divided into 16
Y addresses of 8 lines. Data is read from or written to the 8 lines of X address directly
through DB0 to DB7. The display data of DB0 to DB7 from the microprocessor
correspond to the LCD common lines. The microcomputer can read from and write to
RAM through the I/O buffer. Since the LCD controller operates independently, data
can be written into RAM and displayed at the same time without causing any LCD
flicker.
7.3 Y and X Address Circuits
7.3.1 Y Address Circuit
This circuit incorporates 4-bit Y address register which can only be changed by the “Y
address” instruction. The Y address is set from 0 to 15.
7.3.2 X Address Circuit
This circuit assigns display RAM a line address corresponding to the first line (COM0)
of the display. Therefore, by setting the X address repeatedly, it is possible to scroll the
screen and switch the Y address without changing the contents of the on-chip RAM. It
incorporates the 7-bit Y address register which can only be changed by the initial
display line instruction and the 7-bit counter circuit. At the beginning of each LCD
frame, the contents of the register are copied to the X address counter which is
incremented by the FLM signal. Thus generating the X address for transferring the
128-bit RAM data to the display latch circuit.
The REF select instruction makes it possible to invert the relationship between the X
address and the segment outputs. It is necessary to rewrite the display data on the
built-in RAM after issuing a REF select instruction. See and refer the following Figures
7-5 and 7-6.
16 •
Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
