EM65101
128COM/160SEG 16 Gray Scale Level LCD Driver
SPOL = “0”
Display RAM/Register
Display RAM Data
SPOL = “1”
RS
0
RS
0
Display RAM/Register
Control Register Data
Display RAM Data
1
Control Register Data
1
After completing the 9-bit data transfer, or when making no access, be sure to set the
serial clock input (SCL) to “L.” Care should be taken during PCB layout to avoid
external noise from contaminating the SDA and SCL signals. To prevent any transfer
error due to external noise, release chip select (CSB = “H”) after every complete 9-bit
data transfer.
CSB
RS
D7
D6
D5
D4
D3
D2
D1
D0
SDA
SCL
1
2
3
4
5
6
7
8
9
Figure 7-3 3-Wire Serial Interface
7.2 Writing Data to Display RAM and Control Register
The procedure to write data to the display RAM and Control Register is similar except
for the RS selection to select the accessed object.
RS = “L”: Display RAM data
RS = “H”: Control register data
In the case of the 80-family MPU, data is written at the rising edge of WRB. In the case
of the 68-family MPU, data is written at the falling edge of signal E.
7.2.1 Writing Data Operation
Data5
D7~D0
WRB
Data0
Data1
Data2
Data3
Data4
RS
Write to control register
Write to display RAM
Figure 7-4 Writing Data Operation
Product Specification (V0.4) 08.15.2005
• 15
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
