EM39LV040
4M (512Kx8) Bits Flash Memory
SPECIFICATION
WE# Controlled Sector-Erase Timing Diagram
TSE
Six-Byte Code For Block-Erase
5555
2AAA
5555
5555
2AAA
A18~A0
CE#
SAX
OE#
TWP
WE#
AA
SW0
55
SW1
80
SW2
AA
SW3
55
SW4
50
SW5
DQ7-0
Note: This device also supports CE# controlled Sector-Erase operation. The WE#and CE#
signals are interchageable as long as minimum timings are met. (See Table 10)
SAX=Sector Address
X can be VIL or VIH, but no other value.
Figure 7: WE# Controlled Sector-Erase Timing Diagram
Software ID Entry/Exit and Read
Software ID Entry and Read
Three-Byte Sequence For
Software ID Entry
0000H 0003H 0040H0001H
2AAA
5555
5555
Address A14-0
CE#
OE#
WE#
TIDA
TWP
TAA
7F
TW PH
7F
1F
29h
DQ7-0
55
SW1
90
AA
SW0
SW2
Figure 8: Software ID Entry and Read
This specification is subject to change without further notice. (07.22.2004 V1.0)
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