EM39LV040
4M (512Kx8) Bits Flash Memory
SPECIFICATION
CE# Controlled Program Cycle Timing Diagram
Internal Program Operation Starts
TBP
5555
TAH
2AAA
5555
ADDR
TDS
A18~A0
CE#
TDH
TCP
TCPH
TAS
OE#
WE#
TCH
TCS
DQ7-0
AA
SW0
55
A0
DATA
SW1
SW2
Byte
(ADDR/DATA)
Figure 3: CE# Controlled Program Cycle Timing Diagram
Data# Polling Timing Diagram
A18~A0
TCE
CE#
TOEH
OE#
TOES
TOE
WE#
DATA#
DATA#
DATA#
DATA
DQ7
Figure 4: Data# Polling Timing Diagram
This specification is subject to change without further notice. (07.22.2004 V1.0)
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