EM39LV040
4M (512Kx8) Bits Flash Memory
SPECIFICATION
Timing Diagrams
Read Cycle Timing Diagram
TRC
TAA
A18~A0
CE#
TCE
TOE
OE#
TOHZ
TOLZ
VIH
WE#
TCHZ
TOH
TCLZ
HIGH-Z
HIGH-Z
Data Valid
Data Valid
DQ7-0
Figure 1: Read Cycle Timing Diagram
WE# Controlled Program Cycle Timing Diagram
Internal Program Operation Starts
TBP
5555
TAH
2AAA
5555
ADDR
TDS
A18~A0
WE#
TDH
TWP
TWPH
TAS
OE#
CE#
TCH
TCS
DQ7-0
AA
SW0
55
A0
DATA
SW1
SW2
Byte
(ADDR/DATA)
Figure 2: WE# Controlled Program Cycle Timing Diagram
This specification is subject to change without further notice. (07.22.2004 V1.0)
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