EDS6416AHTA-TI
AC Characteristics (TA = –40 to +85°C, VDD, VDDQ = 3.3V ± 0.3V, VSS, VSSQ = 0V)
-75
Parameter
Symbol
tCK
min.
10
max.
—
Unit
ns
Notes
1
System clock cycle time
(CL = 2)
(CL = 3)
tCK
tCH
tCL
tAC
tOH
tLZ
7.5
2.5
2.5
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
CLK high pulse width
—
1
CLK low pulse width
—
1
Access time from CLK
Data-out hold time
5.4
—
1, 2
1, 2
1, 2, 3
1, 4
1
2
CLK to Data-out low impedance
CLK to Data-out high impedance
Input setup time
0
—
tHZ
tSI
—
5.4
—
1.5
0.8
67.5
45
Input hold time
tHI
—
1
Ref/Active to Ref/Active command period
Active to Precharge command period
tRC
tRAS
—
1
120000
1
Active command to column command
(same bank)
tRCD
20
—
ns
1
Precharge to active command period
Write recovery or data-in to precharge lead time
Last data into active latency
tRP
20
—
—
—
—
5
ns
ns
1
1
tDPL
tDAL
tRRD
tT
15
2CLK + 22.5ns
Active (a) to Active (b) command period
15
ns
ns
1
Transition time (rise and fall)
0.5
Refresh period
(4096 refresh cycles)
tREF
—
64
ms
Notes: 1. AC measurement assumes tT = 0.5ns. Reference level for timing of input signals is 1.4V.
2. Access time is measured at 1.4V. Load condition is CL = 30pF.
3. tLZ (min.) defines the time at which the outputs achieves the low impedance state.
4. tHZ (max.) defines the time at which the outputs achieves the high impedance state.
Preliminary Data Sheet E0636E10 (Ver.1.0)
7
ELPIDA [ ELPIDA MEMORY ]
