EDS6416AHTA-TI
DC Characteristics 1 (TA = –40 to +85°C, VDD, VDDQ = 3.3V ± 0.3V, VSS, VSSQ = 0V)
Parameter
Symbol
IDD1
Grade
max.
100
Unit
mA
Test condition
Burst length = 1
tRC = tRC (min.)
Notes
1, 2, 3
Operating current
CKE = VIL,
Standby current in power down
IDD2P
IDD2PS
IDD2N
IDD2NS
IDD3P
IDD3PS
IDD3N
IDD3NS
IDD4
3
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
6
tCK = tCK (min.)
Standby current in power down
(input signal stable)
2
CKE = VIL, tCK = ∞
7
CKE, /CS = VIH,
tCK = tCK (min.)
CKE = VIH, tCK = ∞,
/CS = VIH
CKE = VIL,
tCK = tCK (min.)
Standby current in non power down
20
9
4
Standby current in non power down
(input signal stable)
8
Active standby current in power down
4
1, 2, 6
2, 7
1, 2, 4
2, 8
1, 2, 5
3
Active standby current in power down
(input signal stable)
3
CKE = VIL, tCK = ∞
CKE, /CS = VIH,
tCK = tCK (min.)
CKE = VIH, tCK = ∞,
/CS = VIH
tCK = tCK (min.),
BL = 4
Active standby current in non power down
35
20
120
220
1.5
Active standby current in non power down
(input signal stable)
Burst operating current
Refresh current
IDD5
tRC = tRC (min.)
VIH ≥ VDD – 0.2V
VIL ≤ 0.2V
Self refresh current
IDD6
Notes: 1. IDD depends on output load condition when the device is selected. IDD (max.) is specified at the output
open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CLK operating current.
7. After power down mode, no CLK operating current.
8. Input signals are VIH or VIL fixed.
Preliminary Data Sheet E0636E10 (Ver.1.0)
5
ELPIDA [ ELPIDA MEMORY ]
