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EDS2516APTA-7AL 参数 Datasheet PDF下载

EDS2516APTA-7AL图片预览
型号: EDS2516APTA-7AL
PDF下载: 下载PDF文件 查看货源
内容描述: 256M位的SDRAM [256M bits SDRAM]
分类和应用: 动态存储器
文件页数/大小: 51 页 / 553 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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EDS2504ACTA/08ACTA/16ACTA, EDS2504APTA/08APTA/16APTA  
DC Characteristics 1 (TA = 0 to +70°C, VDD, VDDQ = 3.3V 0.3V, VSS, VSSQ = 0V)  
Parameter  
max.  
/CAS latency  
Symbol  
ICC1  
Grade  
-7A  
× 4  
× 8  
× 16  
Unit  
mA  
Test condition  
Notes  
1, 2, 3  
Burst length = 1  
tRC = min.  
Burst length = 1  
tRC = min.  
Operating current  
130  
110  
3
130  
135  
ICC1  
-75  
110  
3
115  
3
mA  
mA  
mA  
Standby current in power  
down  
ICC2P  
ICC2PS  
CKE = VIL, tCK = min.  
6
7
Standby current in power  
down (input signal stable)  
2
2
2
CKE = VIL, tCK = ∞  
Standby current in power  
down (input signal stable)  
(EDS2504AP/08AP/16AP)  
(L-version)  
ICC2PS  
ICC2N  
-XXL  
0.5  
0.5  
0.5  
mA  
CKE = VIL, tCK = ∞  
9
Standby current in non  
power down  
CKE, /CS = VIH,  
tCK = min.  
20  
9
20  
9
20  
9
mA  
mA  
mA  
mA  
mA  
mA  
4
8
Standby current in non  
power down (input signal ICC2NS  
stable)  
Active standby current in  
power down  
CKE = VIH, tCK = ,  
/CS = VIH  
ICC3P  
4
4
4
CKE = VIL, tCK = min. 1, 2, 6  
Active standby current in  
power down (input signal ICC3PS  
stable)  
3
3
3
CKE = VIL, tCK = ∞  
2, 7  
Active standby current in  
non power down  
CKE, /CS = VIH,  
tCK = min.  
ICC3N  
30  
15  
30  
15  
30  
15  
1, 2, 4  
2, 8  
Active standby current in  
non power down (input  
signal stable)  
CKE = VIH, tCK = ,  
/CS = VIH  
ICC3NS  
Burst operating current  
Refresh current  
ICC4  
ICC5  
ICC5  
130  
250  
220  
135  
250  
220  
145  
250  
220  
mA  
mA  
mA  
tCK = min., BL = 4  
tRC = min.  
1, 2, 5  
3
-7A  
-75  
tRC = min.  
VIH VDD – 0.2V  
VIL 0.2V  
Self refresh current  
Self refresh current  
(EDS2504AP/08AP/16AP) ICC6  
(L-version)  
ICC6  
3
1
3
1
3
1
mA  
mA  
VIH VDD – 0.2V  
VIL 0.2V  
-XXL  
9
Notes: 1. ICC depends on output load condition when the device is selected. ICC (max.) is specified at the output  
open condition.  
2. One bank operation.  
3. Input signals are changed once per one clock.  
4. Input signals are changed once per two clocks.  
5. Input signals are changed once per four clocks.  
6. After power down mode, CLK operating current.  
7. After power down mode, no CLK operating current.  
8. Input signals are VIH or VIL fixed.  
9. This characteristic is guaranteed only for EDS2504AP/08AP/16AP (L-version).  
Data Sheet E0110E30 (Ver. 3.0)  
5
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