EDS2504ACTA/08ACTA/16ACTA, EDS2504APTA/08APTA/16APTA
DC Characteristics 2 (TA = 0 to +70°C, VDD, VDDQ = 3.3V 0.3V, VSS, VSSQ = 0V)
Parameter
Symbol
ILI
min.
–1
max.
1
Unit
µA
µA
V
Test condition
Notes
Input leakage current
Output leakage current
Output high voltage
Output low voltage
0 ≤ VIN ≤ VDD
ILO
–1.5
2.4
—
1.5
—
0 ≤ VOUT ≤ VDD, DQ = disable
IOH = –4 mA
VOH
VOL
0.4
V
IOL = 4 mA
Pin Capacitance (TA = 25°C, VDD, VDDQ = 3.3V 0.3V)
Notes
Parameter
Symbol
CI1
Pins
CLK
min.
Typ
—
max.
3.5
Unit
pF
1, 2, 4
1, 2, 4
Input capacitance
2.5
2.5
4
Address, CKE, /CS, /RAS,
/CAS, /WE, DQM,
CI2
—
—
3.8
6.5
pF
pF
1, 2, 3, 4
Data input/output capacitance
CI/O
DQ
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. Measurement condition: f = 1MHz, 1.4V bias, 200mV swing.
3. DQM = VIH to disable DOUT.
4. This parameter is sampled and not 100% tested.
AC Characteristics (TA = 0 to +70°C, VDD, VDDQ = 3.3V 0.3V, VSS, VSSQ = 0V)
-7A
-75
Parameter
Symbol
tCK
tCH
tCL
min.
7.5
2.5
2.5
—
min.
7.5
2.5
2.5
—
max.
—
Unit
Notes
System clock cycle time
CLK high pulse width
CLK low pulse width
Access time from CLK
Data-out hold time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
—
1
—
1
tAC
tOH
tLZ
5.4
—
1, 2
1, 2
1, 2, 3
1, 4
1
2.7
1
2.7
1
CLK to Data-out low impedance
CLK to Data-out high impedance
Input setup time
—
tHZ
tSI
—
—
5.4
—
1.5
0.8
60
1.5
0.8
67.5
45
Input hold time
tHI
—
1
Ref/Active to Ref/Active command period tRC
—
1
Active to Precharge command period
tRAS
45
120000
1
Active command to column command
(same bank)
tRCD
tRP
15
15
15
20
20
15
—
—
—
ns
ns
ns
1
1
1
Precharge to active command period
Write recovery or data-in to precharge
lead time
tDPL
tDAL
Last data into active latency
2CLK + 15ns 2CLK + 20ns
—
—
5
Active (a) to Active (b) command period tRRD
15
15
ns
ns
1
Transition time (rise and fall)
tT
0.5
0.5
Refresh period
(8192 refresh cycles)
tREF
—
—
64
ms
Notes: 1. AC measurement assumes tT = 0.5ns. Reference level for timing of input signals is 1.4V.
2. Access time is measured at 1.4V. Load condition is CL = 50pF.
3. tLZ (min.) defines the time at which the outputs achieves the low impedance state.
4. tHZ (max.) defines the time at which the outputs achieves the high impedance state.
Data Sheet E0110E30 (Ver. 3.0)
6
ELPIDA [ ELPIDA MEMORY ]
