DATA SHEET
256M bits SDRAM
EDS2504ACTA, EDS2504APTA (64M words × 4 bits)
EDS2508ACTA, EDS2508APTA (32M words × 8 bits)
EDS2516ACTA, EDS2516APTA (16M words × 16 bits)
Description
Pin Configurations
The EDS2504AC/AP is a 256M bits SDRAM organized
as 16,777,216 words × 4 bits × 4 banks. The EDS2508
AC/AP is a 256M bits SDRAM organized as 8,388,608
words × 8 bits × 4 banks. The EDS2516 AC/AP is a
256M bits SDRAM organized as 4194304 words × 16
bits × 4 banks. All inputs and outputs are referred to
the rising edge of the clock input. It is packaged in
standard 54-pin plastic TSOP (II).
/xxx indicates active low signal.
Index
Index
EDS2504AC/08AC/16AC
EDS2504AP/08AP/16AP
54-pin TSOP
VDD VDD VDD
NC DQ0 DQ0
VDDQ VDDQ VDDQ
VSS VSS VSS
DQ15 DQ7 NC
VSSQ VSSQ VSSQ
DQ14 NC NC
DQ13 DQ6 DQ3
VDDQ VDDQ VDDQ
DQ12 NC NC
DQ11 DQ5 NC
VSSQ VSSQ VSSQ
DQ10 NC NC
DQ9 DQ4 DQ2
VDDQ VDDQ VDDQ
DQ8 NC NC
VSS VSS VSS
1
2
3
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
NC
NC DQ1
4
DQ0 DQ1 DQ2
VSSQ VSSQ VSSQ
5
6
Features
NC
NC DQ3
7
NC DQ2 DQ4
8
VDDQ VDDQ VDDQ
9
• 3.3V power supply
NC
NC DQ5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
• Clock frequency: 133MHz (max.)
• LVTTL interface
DQ1 DQ3 DQ6
VSSQ VSSQ VSSQ
NC
VDD VDD VDD
NC NC LDQM
/WE /WE /WE
/CAS /CAS /CAS
/RAS /RAS /RAS
NC DQ7
• Single pulsed /RAS
NC
NC NC
• 4 banks can operate simultaneously and
independently
UDQM DQM DQM
CLK CLK CLK
CKE CKE CKE
A12 A12 A12
A11 A11 A11
A9
A8
A7
A6
A5
A4
• Burst read/write operation and burst read/single write
operation capability
/CS /CS
/CS
BA0 BA0 BA0
BA1 BA1 BA1
A10 A10 A10
A0
A1
A2
A3
A9
A8
A7
A6
A5
A4
A9
A8
A7
A6
A5
A4
• Programmable burst length* (BL): 1, 2, 4, 8
• 2 variations of burst sequence
Sequential (BL = 1, 2, 4, 8)
A0
A1
A2
A3
A0
A1
A2
A3
Interleave (BL = 1, 2, 4, 8)
VDD VDD VDD
VSS VSS VSS
• Programmable /CAS latency (CL): 2, 3
X 16
X 8
• Byte control by DQM
: DQM (EDS2504AC/AP, EDS2508AC/AP)
: UDQM, LDQM (EDS2516AC/AP)
X 4
• Refresh cycles: 8192 refresh cycles/64ms
• 2 variations of refresh
Auto refresh
(Top view)
A0 to A12, Address input
DQM Input/output mask
CKE Clock enable
BA0, BA1 Bank select address
DQ0 to DQ15 Data-input/output
Self refresh
CLK Clock input
/CS
Chip select
Row address strobe
Column address strobe VDDQ Power for DQ circuit
Write enable VSSQ Ground for DQ circuit
NC No connection
VDD Power for internal circuit
VSS Ground for internal circuit
/RAS
/CAS
/WE
Note: EDS2504AP/08AP/16AP is supported full page
function.
Document No. E0110E30 (Ver. 3.0)
Date Published November 2001 (K) Japan
URL: http://www.elpida.com
C
Elpida Memory, Inc. 2001
ELPIDA [ ELPIDA MEMORY ]
