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EDS1216AABH-75-E 参数 Datasheet PDF下载

EDS1216AABH-75-E图片预览
型号: EDS1216AABH-75-E
PDF下载: 下载PDF文件 查看货源
内容描述: 128M位的SDRAM (8M字×16位) [128M bits SDRAM (8M words x 16 bits)]
分类和应用: 存储内存集成电路动态存储器时钟
文件页数/大小: 49 页 / 694 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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EDS1216AABH, EDS1216CABH  
DQM Control  
The UDQM and LDQM mask the upper and lower bytes of the DQ data, respectively. The timing of UDQM and  
LDQM is different during reading and writing.  
Reading  
When data is read, the output buffer can be controlled by UDQM and LDQM. By setting UDQM and LDQM to Low,  
the output buffer becomes Low-Z, enabling data output. By setting UDQM and LDQM to High, the output buffer  
becomes High-Z, and the corresponding data is not output. However, internal reading operations continue. The  
latency of UDQM and LDQM during reading is 2 clocks.  
Writing  
Input data can be masked by UDQM and LDQM. By setting DQM to Low, data can be written. In addition, when  
UDQM and LDQM are set to High, the corresponding data is not written, and the previous data is held. The latency  
of UDQM and LDQM during writing is 0 clock.  
CLK  
UDQM  
LDQM  
High-Z  
DQ  
out 0  
out 1  
out 3  
lDOD = 2 Latency  
Reading  
CLK  
UDQM  
LDQM  
DQ  
in 3  
in 0  
in 1  
lDID = 0 Latency  
Writing  
Data Sheet E0410E40 (Ver. 4.0)  
38  
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